Custom IC Design

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ELC Error: Redefinition of the subckt

Category: Custom IC Design

By Hemal93

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updated over 9 years ago by Hemal93

2 replies • 14980 views
Discussion

abstract generator: LEF does not contain ANTENNAGATEAREA

Category: Custom IC Design

By jsundermeyer

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updated over 9 years ago by jsundermeyer

2 replies • 16106 views
Discussion

BUG: Drawing path in Virtuoso 6.1.6 only possible in routing layers

Category: Custom IC Design

By Sheppy

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updated over 9 years ago by ColinSutlieff

5 replies • 16057 views
Discussion

Post Layout Simulation Error

Category: Custom IC Design

By sdineshkumar

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updated over 9 years ago by Andrew Beckett

1 replies • 14617 views
Discussion

How to save current through inherited connections in a cell with AMS

Category: Custom IC Design

By twen

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updated over 9 years ago by twen

2 replies • 15695 views
Discussion

How to create dependent voltage source?

Category: Custom IC Design

By BaaB

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updated over 9 years ago by Andrew Beckett

9 replies • 24646 views
Discussion

Assura LVS error

Category: Custom IC Design

By jdgriggs

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updated over 9 years ago by bartman

6 replies • 18358 views
Discussion

Error during the traversal of the config myLib myCell config

Category: Custom IC Design

By twen

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updated over 9 years ago by twen

2 replies • 15784 views
Discussion

Reproduce monte-carlo results with changed netlist

Category: Custom IC Design

By Daniel S

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updated over 9 years ago by Daniel S

2 replies • 14509 views
Discussion

Pin snapping in VirtuosoXL

Category: Custom IC Design

By climbnc

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updated over 9 years ago by ColinSutlieff

1 replies • 14950 views
Discussion

Error found by spectre during circuit read-in--can't find process.scs library

Category: Custom IC Design

By jdgriggs

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updated over 9 years ago by ImanKian

24 replies • 24027 views
Discussion

layout migration

Category: Custom IC Design

By rafaelon

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updated over 9 years ago by ColinSutlieff

1 replies • 15482 views
Discussion

ERROR (SFE-23): "input.scs" 14: N0 is an instance of an undefined model nmos. Tried by adding simulator lang=spice in the first line of the model file

Category: Custom IC Design

By saikishore

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updated over 9 years ago by Andrew Beckett

3 replies • 6638 views
Discussion

Problem in calculation of Power dissipation

Category: Custom IC Design

By raghavendra ks

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updated over 9 years ago by Andrew Beckett

1 replies • 14654 views
Discussion

What's the difference between gate level extraction and transistor level extraction in Calibre xRC tool.

Category: Custom IC Design

By Biasing

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updated over 9 years ago by Biasing

2 replies • 11979 views

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