Custom IC Design

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Search for all instances of a specific cell within a hierarchy

Category: Custom IC Design

By Kevin Buck

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updated over 4 years ago by FormerMember

3 replies • 13920 views
Discussion

different results from spice in

Category: Custom IC Design

By MReza123

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updated over 4 years ago by MReza123

2 replies • 10893 views
Discussion

veriloga integer input to 32-bit address output has a strnage error/how to debug/where to find the latest veriloga reference documents?

Category: Custom IC Design

By monglebest

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updated over 4 years ago by monglebest2022

5 replies • 4451 views
Discussion

Run Monte Carlo with ADE Explorer

Category: Custom IC Design

By lxc123

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updated over 4 years ago by lxc123

3 replies • 14497 views
Discussion

spicein different results

Category: Custom IC Design

By closyx

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updated over 4 years ago by Andrew Beckett

1 replies • 10069 views
Discussion

Matlab interfacing with Virtuoso

Category: Custom IC Design

By sidm

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updated over 4 years ago by Andrew Beckett

11 replies • 15973 views
Discussion

Loading simulation results into maestro explorer/assembler

Category: Custom IC Design

By Svilen64

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updated over 4 years ago by Andrew Beckett

3 replies • 4382 views
Discussion

Quantizing sine wave

Category: Custom IC Design

By Farhan Ali 9216

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updated over 4 years ago by Andrew Beckett

4 replies • 14887 views
Discussion

Modifying/Editing Maestro/Assembler Test setup with text editor

Category: Custom IC Design

By greywanderer

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updated over 4 years ago by greywanderer

4 replies • 2982 views
Discussion

supported psf format different between IC617 and IC618?

Category: Custom IC Design

By kkdesbois

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updated over 4 years ago by kkdesbois

2 replies • 10733 views
Discussion

Why pin object is converted to shape in Abstract generator

Category: Custom IC Design

By knowledgeseeker

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updated over 4 years ago by Andrew Beckett

1 replies • 9920 views
Discussion

How to find "file signature" of design files in Cadence Virtuoso (schematics, layouts, symbols, etc.)

Category: Custom IC Design

By Cocacola

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updated over 4 years ago by Andrew Beckett

6 replies • 3355 views
Discussion

Transient simulation termination by VerilogA model

Category: Custom IC Design

By Senan

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updated over 4 years ago by Senan

4 replies • 12626 views
Discussion

Verilog Error

Category: Custom IC Design

By Lemi

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updated over 4 years ago by Andrew Beckett

1 replies • 12856 views
Discussion

Layer Generation of Multiple Layers in Virtuoso

Category: Custom IC Design

By Tom Sawyer

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updated over 4 years ago by Andrew Beckett

10 replies • 14894 views

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