Custom IC Design

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Discussion

Spectre: is it possible to define a deterministic start time for the PSS beat period?

Category: Custom IC Design

By dontpanic

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updated over 3 years ago by Andrew Beckett

2 replies • 10782 views
Discussion

Quantus: extraction to DSPF fails if "Delete X prefix" option is used

Category: Custom IC Design

By dontpanic

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updated over 3 years ago by dontpanic

2 replies • 2527 views
Discussion

Simulating Config with veriloga view set, does not simulate the veriloga version but still runs the schematic.

Category: Custom IC Design

By JohnTweed

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updated over 3 years ago by JohnTweed

12 replies • 14989 views
Discussion

Virtuoso Schematic Bus Connection

Category: Custom IC Design

By RaphaelN

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updated over 3 years ago by Andrew Beckett

4 replies • 14573 views
Discussion

Running ocean jobs without starting X server

Category: Custom IC Design

By ebecheto

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updated over 3 years ago by Andrew Beckett

1 replies • 8654 views
Discussion

Is it possible to change the icons on the taskbar/panel?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 1014 views
Discussion

how to check netlist when using LSCS mode

Category: Custom IC Design

By sjwprcker

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updated over 3 years ago by Andrew Beckett

1 replies • 8619 views
Discussion

Printing noise summary to file for specific corner/sweep point

Category: Custom IC Design

By brianbranch

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started over 3 years ago

0 replies • 1309 views
Discussion

Assembler: Evaluating output expressions from suspended, but completed simulations

Category: Custom IC Design

By fyoh

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updated over 3 years ago by fyoh

2 replies • 8643 views
Discussion

connectivity in layout

Category: Custom IC Design

By paulinho

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updated over 3 years ago by Andrew Beckett

1 replies • 10151 views
Discussion

What are the symptoms that the "auto adjustment" function is not activated for some transistors?

Category: Custom IC Design

By Daeho

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updated over 3 years ago by Daeho

2 replies • 1032 views
Discussion

How to increase the precision of signal [Verilog-A problem]?

Category: Custom IC Design

By YYLee

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updated over 3 years ago by YYLee

2 replies • 9497 views
Discussion

Assembler Results table in Detailed Transposed mode cuts the output names ic20.1.500.22

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by Andrew Beckett

1 replies • 8331 views
Discussion

How can I combine Multipart Path from several .il files?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

9 replies • 11161 views
Discussion

I want the layout view to be automatically displayed on the left.

Category: Custom IC Design

By Daeho

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updated over 3 years ago by Daeho

2 replies • 9476 views

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