Custom IC Design

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Issue with autogenerating multiple Verilog-A views in same cell

Category: Custom IC Design

By muheicdesign

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updated over 2 years ago by Andrew Beckett

3 replies • 7659 views
Discussion

DSPF black box

Category: Custom IC Design

By Pirate King

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updated over 2 years ago by Ashwin Rebello

3 replies • 9704 views
Discussion

pointer precision in cadence virtuoso layout XL

Category: Custom IC Design

By ISHITA AGGARWAL

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updated over 2 years ago by ISHITA AGGARWAL

2 replies • 7327 views
Discussion

spextreX accuracy preset as dynamic parameter

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by Andrew Beckett

1 replies • 6499 views
Discussion

cmdmprobe from analogLib

Category: Custom IC Design

By illaoi

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updated over 2 years ago by ShawnLogan

7 replies • 11460 views
Discussion

Wrong keyboard mapping

Category: Custom IC Design

By Kurt63

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updated over 2 years ago by Kurt63

4 replies • 8684 views
Discussion

What does Noise Contribution Option in transient simulation mean?

Category: Custom IC Design

By Leo66

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updated over 2 years ago by Leo66

2 replies • 8511 views
Discussion

Is it required a particular license to plot internal VerilogA parameters?

Category: Custom IC Design

By Rawcode

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updated over 2 years ago by Rawcode

11 replies • 10441 views
Discussion

Instance bBox vs Flattened bBox

Category: Custom IC Design

By Chanyou

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updated over 2 years ago by Chanyou

1 replies • 6303 views
Discussion

how to set the default number of digits in the sim log

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by sjwprcker

2 replies • 6911 views
Discussion

will the phase of the pss period affect sampled pnoise result? can I control the pss phase?

Category: Custom IC Design

By Ring Lewis

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updated over 2 years ago by Ring Lewis

2 replies • 7178 views
Discussion

Running corner PVT sims with scalar output evaluated but waveforms not saved

Category: Custom IC Design

By SunnyBhagia

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updated over 2 years ago by ShawnLogan

4 replies • 7481 views
Discussion

error in digital verilog code

Category: Custom IC Design

By blossom

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updated over 2 years ago by Andrew Beckett

2 replies • 8358 views
Discussion

How to replace the device instance numbers

Category: Custom IC Design

By ichiro

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updated over 2 years ago by Andrew Beckett

3 replies • 7205 views
Discussion

Font Size for Trace Info Overlay in ViVA

Category: Custom IC Design

By jdsherman

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updated over 2 years ago by Andrew Beckett

2 replies • 6644 views

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