Custom IC Design

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Stability check issue during phase starting with 0 degree

Category: Custom IC Design

By MIN KIM

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updated over 6 years ago by Frank Wiedmann

3 replies • 19759 views
Discussion

Stability factor of differential LNA

Category: Custom IC Design

By Qusai

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updated over 6 years ago by FormerMember

7 replies • 19416 views
Discussion

Transient Violations taking too much disk space

Category: Custom IC Design

By ChrisG04

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updated over 6 years ago by ChrisG04

2 replies • 15942 views
Discussion

ADE Explorer switch view list

Category: Custom IC Design

By FormerMember

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updated over 6 years ago by Andrew Beckett

3 replies • 6768 views
Discussion

LVS error

Category: Custom IC Design

By sjeur

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updated over 6 years ago by Andrew Beckett

3 replies • 15002 views
Discussion

ADE L problem

Category: Custom IC Design

By Archon

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updated over 6 years ago by Andrew Beckett

3 replies • 15705 views
Discussion

annotating parasitics from Calibre PEX netlist to layout or schematic

Category: Custom IC Design

By haritha8085

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updated over 6 years ago by Andrew Beckett

1 replies • 15269 views
Discussion

cross probing between layout and schematic

Category: Custom IC Design

By haritha8085

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updated over 6 years ago by Andrew Beckett

1 replies • 15038 views
Discussion

Parametric simulation in Cadence ADEXL

Category: Custom IC Design

By NorNand

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updated over 6 years ago by Andrew Beckett

5 replies • 19496 views
Discussion

floating metal check in layout

Category: Custom IC Design

By DavidLou

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updated over 6 years ago by DavidLou

4 replies • 17190 views
Discussion

avoid local alteration on iterative instances

Category: Custom IC Design

By giopero

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updated over 6 years ago by giopero

2 replies • 14208 views
Discussion

modeling output impedance in a file

Category: Custom IC Design

By dzakharian

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updated over 6 years ago by dzakharian

2 replies • 14999 views
Discussion

VAR function output slowly

Category: Custom IC Design

By Franktgg

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updated over 6 years ago by Andrew Beckett

1 replies • 13855 views
Discussion

Accessing data vector generated by a Virtuoso expression in Matlab using adeInfo

Category: Custom IC Design

By Cra1g

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updated over 6 years ago by Andrew Beckett

3 replies • 16563 views
Discussion

verilogA timestep dynamic management

Category: Custom IC Design

By Fabb

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updated over 6 years ago by Andrew Beckett

5 replies • 20443 views

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