Custom IC Design

Latest Posts

Discussion

How to override the default values using Verilog netlist.

Category: Custom IC Design

By Omar Ghazal

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updated over 1 year ago by Omar Ghazal

4 replies • 4868 views
Discussion

simulating quadrature oscillator

Category: Custom IC Design

By soroush7492

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started over 1 year ago

0 replies • 3545 views
Discussion

Excluding Devices from Quantus RC Extraction

Category: Custom IC Design

By sgcad

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started over 1 year ago

0 replies • 3625 views
Discussion

Different results with different simulators

Category: Custom IC Design

By Doronzzz

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started over 1 year ago

0 replies • 3637 views
Discussion

Variable multiplicity factor("m") for different instances of the same cellview in Cadence Virtuoso

Category: Custom IC Design

By Saumeek

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updated over 1 year ago by Andrew Beckett

1 replies • 1113 views
Discussion

Save to CSV results of DC Sweep simulation.

Category: Custom IC Design

By IKIF

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started over 1 year ago

0 replies • 3402 views
Discussion

Virtuoso version update issue

Category: Custom IC Design

By baobov587

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updated over 1 year ago by baobov587

2 replies • 4478 views
Discussion

Maestro - device parameter as variable

Category: Custom IC Design

By firebolt3

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updated over 1 year ago by Andrew Beckett

1 replies • 1944 views
Discussion

Use variation for sweep different files in AMS simulation

Category: Custom IC Design

By nonameirvine

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updated over 1 year ago by Andrew Beckett

1 replies • 3621 views
Discussion

different simulation results issue

Category: Custom IC Design

By oweny

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updated over 1 year ago by Andrew Beckett

1 replies • 3927 views
Discussion

Maestro - auto update & run the unsaved schematic

Category: Custom IC Design

By firebolt3

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updated over 1 year ago by Andrew Beckett

1 replies • 660 views
Discussion

modify the font size in virtuoso

Category: Custom IC Design

By AB_1716146146878

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updated over 1 year ago by RobMan

1 replies • 7279 views
Discussion

Explorer to run an AMS simulation by copying the files rather than using their absolute path

Category: Custom IC Design

By Pedro P

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started over 1 year ago

0 replies • 3648 views
Discussion

Create schematic from netlist(verilog)

Category: Custom IC Design

By SimhanAnalog

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updated over 1 year ago by SimhanAnalog

2 replies • 1871 views
Discussion

Export layout from Layout XL

Category: Custom IC Design

By overmach

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updated over 1 year ago by Andrew Beckett

5 replies • 5202 views

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