Custom IC Design

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Discussion

Cadence ADEXL: how to merge troubleshot point with rest of montecarlo data

Category: Custom IC Design

By spectrallypure

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updated over 12 years ago by Frank Wiedmann

12 replies • 20521 views
Discussion

skill to plot waveform contained in a file into w-viewer (could be VIVA)

Category: Custom IC Design

By azde

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updated over 12 years ago by Andrew Beckett

3 replies • 14533 views
Discussion

Is there a way to print model parameter using Hspice-D version2012.03 after running a simulation?

Category: Custom IC Design

By Alex Liao

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updated over 12 years ago by Andrew Beckett

9 replies • 20559 views
Discussion

STB analysis stops running ... with no error in output.log

Category: Custom IC Design

By Praveen K

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updated over 12 years ago by Praveen K

2 replies • 15315 views
Discussion

Ghost of Dragged object

Category: Custom IC Design

By Anonymous

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updated over 12 years ago by Anonymous

2 replies • 13840 views
Discussion

How to search for vias with rows or columsn property in layout XL

Category: Custom IC Design

By pham777

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updated over 12 years ago by pham777

6 replies • 15794 views
Discussion

operating points implementation (verilogA and CDF)

Category: Custom IC Design

By Fabb

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updated over 12 years ago by Andrew Beckett

3 replies • 14180 views
Discussion

importing EDIF file (library install)

Category: Custom IC Design

By oldnick

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updated over 12 years ago by oldnick

2 replies • 17561 views
Discussion

verilogin problem: modules are imported twice

Category: Custom IC Design

By Howel

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updated over 12 years ago by Howel

2 replies • 14652 views
Discussion

Virtuoso Strmout of selected cells

Category: Custom IC Design

By Stevemc12

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updated over 12 years ago by Andrew Beckett

3 replies • 15906 views
Discussion

ADE XL job dispatch behavior (LSF)

Category: Custom IC Design

By kentauta

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updated over 12 years ago by Andrew Beckett

1 replies • 15571 views
Discussion

Force ams netlister to skip ports/pins

Category: Custom IC Design

By Runner

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updated over 12 years ago by Andrew Beckett

1 replies • 1121 views
Discussion

How to attach the cdl netlist with cdl view

Category: Custom IC Design

By scorashu

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updated over 12 years ago by Andrew Beckett

1 replies • 20084 views
Discussion

DRC and LVS error

Category: Custom IC Design

By samanehrh

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updated over 12 years ago by Andrew Beckett

1 replies • 14070 views
Discussion

Have problem in simulating circuit in virtuoso ADE

Category: Custom IC Design

By sunilreddy

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updated over 12 years ago by Andrew Beckett

3 replies • 14431 views

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