Custom IC Design

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"Assura has not been installed in this hierarchy" Error

Category: Custom IC Design

By nokta

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updated over 6 years ago by nokta

2 replies • 3623 views
Discussion

use output signals from other circuits as input for simulation

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Andrew Beckett

3 replies • 15786 views
Discussion

Setting TimeStep for Transient simulations : defaulting to ps

Category: Custom IC Design

By HariV

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updated over 6 years ago by FormerMember

3 replies • 23320 views
Discussion

Dynamic nodesets on DC Sweeps

Category: Custom IC Design

By Johanny Saenz

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updated over 6 years ago by Andrew Beckett

1 replies • 13878 views
Discussion

Unable to do some functions in the layout. Getting Errors

Category: Custom IC Design

By Bala Sowjanya

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updated over 6 years ago by Andrew Beckett

1 replies • 13911 views
Discussion

Sweeping different design variables at the same time within an (qpss) analysis

Category: Custom IC Design

By Emiel

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updated over 6 years ago by Andrew Beckett

3 replies • 15323 views
Discussion

shortcut to bring ADE with current schematic to front

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Andrew Beckett

20 replies • 20053 views
Discussion

Parallelizing simulation with a variable sweep in an analysis itself

Category: Custom IC Design

By Emiel

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updated over 6 years ago by Andrew Beckett

1 replies • 14417 views
Discussion

how to define different sweep variables for different test within the same adexl

Category: Custom IC Design

By Karev11

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updated over 6 years ago by Andrew Beckett

3 replies • 15609 views
Discussion

Abstract physical information file (.LEF) of standard cell

Category: Custom IC Design

By fengye

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updated over 6 years ago by fengye

9 replies • 18819 views
Discussion

CSF search mechanism - load .cdsinit from $HOME even if its disabled in setup.loc

Category: Custom IC Design

By HoWei

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updated over 6 years ago by Andrew Beckett

12 replies • 9607 views
Discussion

the color of instance label in symbol editor

Category: Custom IC Design

By zssfred

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updated over 6 years ago by zssfred

3 replies • 15657 views
Discussion

Layout versus Schematic design issue

Category: Custom IC Design

By NorNand

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updated over 6 years ago by Andrew Beckett

4 replies • 15835 views
Discussion

Plotting VerilogA String Variables

Category: Custom IC Design

By Tjaart

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updated over 6 years ago by Andrew Beckett

4 replies • 16284 views
Discussion

Monte Carlo simulation of noise contributions using SpectreMDL

Category: Custom IC Design

By svcher

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updated over 6 years ago by svcher

2 replies • 14444 views

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