Custom IC Design

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Discussion

how to create a via in pcell?

Category: Custom IC Design

By TZ20240722725

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started 8 months ago

0 replies • 1848 views
Discussion

Passing Global Variable to Matlab function

Category: Custom IC Design

By eyalg

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started 8 months ago

0 replies • 1803 views
Discussion

Inductor in Cadence Virtuoso

Category: Custom IC Design

By Nalaeg

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updated 8 months ago by Nalaeg

3 replies • 3105 views
Discussion

Where to Find the Script That Defines Default Corner Settings in a New Maestro View?

Category: Custom IC Design

By baltaci

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updated 8 months ago by Andrew Beckett

1 replies • 2163 views
Discussion

SPICEIN for importing netlisting with pPar expressions

Category: Custom IC Design

By PSKR

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updated 8 months ago by Andrew Beckett

1 replies • 2307 views
Discussion

Metric Prefix

Category: Custom IC Design

By samirc

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updated 8 months ago by Andrew Beckett

1 replies • 2091 views
Discussion

Open Design in Assembler Test can cause overwriting of the design

Category: Custom IC Design

By StephanWeber

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updated 8 months ago by StephanWeber

4 replies • 2332 views
Discussion

veriloga error between spectre and ams

Category: Custom IC Design

By SimhanAnalog

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updated 8 months ago by SimhanAnalog

4 replies • 2811 views
Discussion

sampled PAC transfer function to discrete step response

Category: Custom IC Design

By david73

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started 8 months ago

0 replies • 1906 views
Discussion

Stability Analysis of a Ramp Generator Circuit in Integration Phase

Category: Custom IC Design

By baltaci

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updated 8 months ago by StephanWeber

4 replies • 2987 views
Discussion

PAM4 eye diagrams in Cadence

Category: Custom IC Design

By TUKA

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updated 8 months ago by TUKA

2 replies • 2735 views
Discussion

Schematic pin highlight

Category: Custom IC Design

By SimhanAnalog

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updated 8 months ago by Andrew Beckett

2 replies • 2880 views
Discussion

How to Toggle Metal Layer Visibility Sequentially with Bindkeys?

Category: Custom IC Design

By SS202502085313

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updated 8 months ago by Andrew Beckett

3 replies • 2733 views
Discussion

Control position of instance placement in an ihdl imported schematic

Category: Custom IC Design

By mrharris

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updated 8 months ago by Andrew Beckett

1 replies • 2104 views
Discussion

Finding EAD/ICT file for running parasitic Extraction in Virtuoso EXL

Category: Custom IC Design

By AL202502074331

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updated 8 months ago by Andrew Beckett

1 replies • 668 views

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