Custom IC Design

Latest Posts

Discussion

How can I combine Multipart Path from several .il files?

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by Andrew Beckett

9 replies • 11170 views
Discussion

I want the layout view to be automatically displayed on the left.

Category: Custom IC Design

By Daeho

$usertype
•
updated over 3 years ago by Daeho

2 replies • 9482 views
Discussion

psf utility

Category: Custom IC Design

By Driss

$usertype
•
updated over 3 years ago by FormerMember

2 replies • 11615 views
Discussion

Cadence GPDKs Installation Guide

Category: Custom IC Design

By tesla123

$usertype
•
updated over 3 years ago by tesla123

2 replies • 13484 views
Discussion

Issue with importing csv file to the ADEXL outputs

Category: Custom IC Design

By greywanderer

$usertype
•
updated over 3 years ago by greywanderer

12 replies • 12628 views
Discussion

How can I avoid ADE outputs like 33 m% of 120 mdB?

Category: Custom IC Design

By StephanWeber

$usertype
•
updated over 3 years ago by StephanWeber

6 replies • 9584 views
Discussion

IC design from basics

Category: Custom IC Design

By Hassan Irshad

$usertype
•
started over 3 years ago

0 replies • 7876 views
Discussion

comparison of two design points in a variable sweep

Category: Custom IC Design

By FormerMember

$usertype
•
updated over 3 years ago by Andrew Beckett

3 replies • 5287 views
Discussion

How to check the load capacitance of a node in cadence virtuoso?

Category: Custom IC Design

By zuiying

$usertype
•
updated over 3 years ago by Andrew Beckett

6 replies • 23985 views
Discussion

Net Highlighting without appearing staggered lines

Category: Custom IC Design

By billgzhsu

$usertype
•
updated over 3 years ago by billgzhsu

6 replies • 11537 views
Discussion

Copy single test between ADE Assembler maestro files?

Category: Custom IC Design

By TempViator

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 10540 views
Discussion

parasitic exclusion not working in PAD

Category: Custom IC Design

By Pirate King

$usertype
•
updated over 3 years ago by Pirate King

1 replies • 8551 views
Discussion

Wire Assistant in layout loosing connectivity

Category: Custom IC Design

By Senan

$usertype
•
updated over 3 years ago by Senan

4 replies • 10284 views
Discussion

LVS Port Mismatch Errors with CDL Netlist

Category: Custom IC Design

By amrao

$usertype
•
updated over 3 years ago by Andrew Beckett

3 replies • 11724 views
Discussion

How to use a CSV file in Cadence?

Category: Custom IC Design

By Sachin Mishra

$usertype
•
updated over 3 years ago by Sachin Mishra

6 replies • 20259 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.