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Custom IC Design

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  • Discussion

    layout XL extract cellviews in hierarchy?

    Category: Custom IC Design

    By yeh1

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    started over 7 years ago

    0 replies • 13546 views
  • Discussion

    import spice net list created from calibre lvs tool

    Category: Custom IC Design

    By programzombie

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    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 14353 views
  • Discussion

    detecting process corner from within verilogA model

    Category: Custom IC Design

    By SoniaMK

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    updated over 7 years ago by Saloni Chhabra

    20 replies • 24207 views
  • Discussion

    auCDL, question about ansCdlSubcktCall netlist procedure!

    Category: Custom IC Design

    By MedAn

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    •

    updated over 7 years ago by Andrew Beckett

    2 replies • 15920 views
  • Discussion

    Ocean command to access the result stored during Monte-carlo Simulation

    Category: Custom IC Design

    By Ishant Anand

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    updated over 7 years ago by Andrew Beckett

    3 replies • 15302 views
  • Discussion

    Deleting multiple instances of a cell from Layout

    Category: Custom IC Design

    By kash022

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    updated over 7 years ago by kash022

    4 replies • 16619 views
  • Discussion

    Schematic editor: how to change the color of the annotations?

    Category: Custom IC Design

    By dontpanic

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    updated over 7 years ago by dontpanic

    2 replies • 17042 views
  • Discussion

    Plot Schematic Hierarchy into single file

    Category: Custom IC Design

    By HoWei

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    updated over 7 years ago by HoWei

    3 replies • 15882 views
  • Discussion

    Monte Carlo simulation results have difference even in ideal circuits

    Category: Custom IC Design

    By sam jiang

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    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 13490 views
  • Discussion

    How to add/configure new column in Monte Carlo result page (Summary & Yield), like Std Dev/mean

    Category: Custom IC Design

    By sjwprc

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    updated over 7 years ago by Andrew Beckett

    1 replies • 684 views
  • Discussion

    How to write Monte Carlo file for FinFET?

    Category: Custom IC Design

    By Amin Zayed

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    updated over 7 years ago by Andrew Beckett

    1 replies • 13369 views
  • Discussion

    Reversing the contents of an expanded bus in VIVA

    Category: Custom IC Design

    By CADcasualty

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    •

    updated over 7 years ago by Andrew Beckett

    2 replies • 13885 views
  • Discussion

    Documentation error for awvPlotWaveform function in Virtuoso Visualization and Analysis XL SKILL Reference manual

    Category: Custom IC Design

    By CADcasualty

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    •

    updated over 7 years ago by Andrew Beckett

    2 replies • 13571 views
  • Discussion

    Simulation and PEX

    Category: Custom IC Design

    By AllenD

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    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 15954 views
  • Discussion

    RE: IBIS Version 6.1

    Category: Custom IC Design

    By kenambo

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    •

    started over 7 years ago

    0 replies • 12878 views
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