Custom IC Design

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asimenv mappingMode

Category: Custom IC Design

By yeh1

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updated over 8 years ago by Andrew Beckett

1 replies • 13362 views
Discussion

Using OPTION SCALE for only a particuar instance in Virtuoso ADE

Category: Custom IC Design

By jdp721

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updated over 8 years ago by jdp721

4 replies • 17625 views
Discussion

AMS simulator with APS and multi-thread

Category: Custom IC Design

By SteveRFIC

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updated over 8 years ago by Andrew Beckett

4 replies • 19876 views
Discussion

GDS streamed out data different from my actual layout in virtuoso

Category: Custom IC Design

By prayo

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updated over 8 years ago by Andrew Beckett

1 replies • 13323 views
Discussion

DC bias operating point, IC6.14, MMSIM10

Category: Custom IC Design

By Kabal

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updated over 8 years ago by Quek

10 replies • 20491 views
Discussion

How to delete lock files after cell is closed?

Category: Custom IC Design

By Kabal

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updated over 8 years ago by Andrew Beckett

4 replies • 25683 views
Discussion

Symbol line disappear in schematic view

Category: Custom IC Design

By happymos123

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updated over 8 years ago by Andrew Beckett

3 replies • 14757 views
Discussion

ddAutoCheckIn during strmin

Category: Custom IC Design

By JayR

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updated over 8 years ago by Quek

3 replies • 13525 views
Discussion

Choosing a CPU for best ADE performance

Category: Custom IC Design

By wahidr

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updated over 8 years ago by Quek

1 replies • 15850 views
Discussion

List of latches used in netlist ?

Category: Custom IC Design

By roopakvasa

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updated over 8 years ago by Quek

1 replies • 13295 views
Discussion

Calibre LVS with simulated sonnet component

Category: Custom IC Design

By Juanelin

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updated over 8 years ago by Quek

1 replies • 14621 views
Discussion

changing via using skill

Category: Custom IC Design

By GirishBS181

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updated over 8 years ago by GirishBS181

2 replies • 14261 views
Discussion

Path drawn in Cadence Vituoso Layout Editor seems to get attached with adjacent Via

Category: Custom IC Design

By jdp721

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updated over 8 years ago by jdp721

2 replies • 15553 views
Discussion

why is the input referred noise not proportional to the output noise?

Category: Custom IC Design

By MarcoL

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updated over 8 years ago by MarcoL

5 replies • 4208 views
Discussion

Running an external shell script from within a Verilog-a block

Category: Custom IC Design

By mwb1

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updated over 8 years ago by chanakaya

1 replies • 13780 views

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