Custom IC Design

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Discussion

Only a functional file was created after using generate in Verilog

Category: Custom IC Design

By RuihW

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updated over 2 years ago by Andrew Beckett

3 replies • 7287 views
Discussion

Input File for Vsource in Cadence Virtuoso

Category: Custom IC Design

By Maverick007

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updated over 2 years ago by Andrew Beckett

4 replies • 9179 views
Discussion

problem with CDF

Category: Custom IC Design

By Mdad

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updated over 2 years ago by Andrew Beckett

2 replies • 6688 views
Discussion

how to create lookup table VCVS in SPECTRE

Category: Custom IC Design

By Frank Cano

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updated over 2 years ago by Andrew Beckett

4 replies • 7801 views
Discussion

CUVHNF error in ams simulation

Category: Custom IC Design

By sjwprcker

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started over 2 years ago

0 replies • 5973 views
Discussion

Why VXL generates a pin with "1_" prefix?

Category: Custom IC Design

By kenc184

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updated over 2 years ago by kenc184

1 replies • 712 views
Discussion

How to save only the power information of certain circuits?

Category: Custom IC Design

By zuiying

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updated over 2 years ago by zuiying

8 replies • 8742 views
Discussion

How to get around 'no library changes' in Config views?

Category: Custom IC Design

By TempViator

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updated over 2 years ago by TempViator

2 replies • 1527 views
Discussion

Get Hierarchy Editor to bind schematic and symbol views

Category: Custom IC Design

By TempViator

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updated over 2 years ago by Andrew Beckett

1 replies • 6300 views
Discussion

How to save power signals in XPS MS simulation?

Category: Custom IC Design

By zuiying

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updated over 2 years ago by Andrew Beckett

1 replies • 6146 views
Discussion

DEF input and output frim Virtuoso

Category: Custom IC Design

By BrJaWr

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started over 2 years ago

0 replies • 6763 views
Discussion

select from overlaps?

Category: Custom IC Design

By kenc184

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updated over 2 years ago by RobMan

3 replies • 6574 views
Discussion

No DRC Error, still seeing the cross on the layers?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Vishesh Gupta

2 replies • 7382 views
Discussion

skill function to get name of test defined in ADE assembler

Category: Custom IC Design

By Ejcxuralsshdd

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updated over 2 years ago by ShawnLogan

1 replies • 6483 views
Discussion

deepprobe to access verilogA

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by Andrew Beckett

1 replies • 7188 views

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