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Custom IC Design

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  • Discussion

    Can I analyze LDE effects on finfet design using GPDK cds_ff_mpt_v_0.5

    Category: Custom IC Design

    By mehrnazi

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    started over 5 years ago

    0 replies • 13203 views
  • Discussion

    Verilog-A Simulation

    Category: Custom IC Design

    By Suhas7

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 14223 views
  • Discussion

    Instance terminal mapping within IC5.10.41.500.x.x running on RHEl6.9

    Category: Custom IC Design

    By PBWU

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    •

    updated over 5 years ago by PBWU

    4 replies • 13844 views
  • Discussion

    Pnoise vs Transient noise

    Category: Custom IC Design

    By Haoyi219

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    •

    updated over 5 years ago by Haoyi219

    2 replies • 18810 views
  • Discussion

    Pass veriloga parameter to parameters in ADE XL

    Category: Custom IC Design

    By JakobToft

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    •

    updated over 5 years ago by JakobToft

    4 replies • 18355 views
  • Discussion

    How to measure the performance of a PLL ?

    Category: Custom IC Design

    By JJJin

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    •

    started over 5 years ago

    0 replies • 13306 views
  • Discussion

    Dynamic temperature variation of a SPECIFIC component during transient simulation

    Category: Custom IC Design

    By Quantum7

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    •

    updated over 5 years ago by Andrew Beckett

    3 replies • 15743 views
  • Discussion

    Using DFT to analyze a time-interleaving track and hold circuit

    Category: Custom IC Design

    By YutaoLiu

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    updated over 5 years ago by Andrew Beckett

    1 replies • 14149 views
  • Discussion

    How do make the clock 25% duty cycle with jitter capability

    Category: Custom IC Design

    By cADEUser

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    updated over 5 years ago by Andrew Beckett

    4 replies • 17025 views
  • Discussion

    How to generate a clock signal with random noise in Cadence Spectre?

    Category: Custom IC Design

    By BackerShu

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    updated over 5 years ago by Andrew Beckett

    3 replies • 29053 views
  • Discussion

    Method to scale up or down lots of resistor/capacitor value together

    Category: Custom IC Design

    By FormerMember

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    updated over 5 years ago by henker

    1 replies • 2306 views
  • Discussion

    Mixed-signal CDL netlist export

    Category: Custom IC Design

    By Nicolas Callens

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 15191 views
  • Discussion

    LDO design and simulation

    Category: Custom IC Design

    By SHATADAL IIITG

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    •

    started over 5 years ago

    0 replies • 13967 views
  • Discussion

    Smooth dynamic parameter variation in transient sim

    Category: Custom IC Design

    By Quantum7

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 15070 views
  • Discussion

    Plotting temperature in a transient simulation

    Category: Custom IC Design

    By Quantum7

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    •

    updated over 5 years ago by Quantum7

    9 replies • 20618 views
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