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Custom IC Design

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  • Discussion

    Plotting DC results - bus Y values vs. bus X values

    Category: Custom IC Design

    By mikewu999 mikewu999

    •

    updated 9 months ago by mikewu999

    1 replies • 520 views
  • Discussion

    How to deal with multiple Vsupplys in AMS IE-Card

    Category: Custom IC Design

    By SpiceMonkey SpiceMonkey

    •

    started 9 months ago

    0 replies • 2014 views
  • Discussion

    Clarification on Simulation Failures with Max. Jobs > 1 in ADE Assembler

    Category: Custom IC Design

    By baltaci baltaci

    •

    started 9 months ago

    0 replies • 725 views
  • Discussion

    How to run Assura Open Run from the command line?

    Category: Custom IC Design

    By LoVyacheslavvVEMs LoVyacheslavvVEMs

    •

    started 9 months ago

    0 replies • 1995 views
  • Discussion

    Clicking Check and Save in Verilog Editor of Virtuoso returns error 'Extract Failed for Cellview"

    Category: Custom IC Design

    By DK202409295316 DK202409295316

    •

    started 9 months ago

    0 replies • 1247 views
  • Discussion

    Celsius CFD Crashing after clicking simulation button

    Category: Custom IC Design

    By HSDROP HSDROP

    •

    started 9 months ago

    0 replies • 1941 views
  • Discussion

    How to Set Up a Config View to Easily Switch Between Schematic and Calibre of DUT for Multiple Testbenches?

    Category: Custom IC Design

    By Meraj Ahmad Meraj Ahmad

    •

    updated 9 months ago by Meraj Ahmad

    2 replies • 3578 views
  • Discussion

    AMS simvision cannot load big psf.trn

    Category: Custom IC Design

    By gkasap92 gkasap92

    •

    started 9 months ago

    0 replies • 2083 views
  • Discussion

    Force virtuoso (Layout XL) to NOT create warning markers in design

    Category: Custom IC Design

    By CSCNalu CSCNalu

    •

    updated 9 months ago by RobMan

    2 replies • 3194 views
  • Discussion

    Characterization of Full adder that use transmission gates using liberate

    Category: Custom IC Design

    By TM20240913386 TM20240913386

    •

    updated 9 months ago by TM20240913386

    1 replies • 2495 views
  • Discussion

    error when generating snp files from a variable

    Category: Custom IC Design

    By TommasoF TommasoF

    •

    updated 9 months ago by TommasoF

    3 replies • 2693 views
  • Discussion

    ddt VerilogA usage

    Category: Custom IC Design

    By AndreaD AndreaD

    •

    started 9 months ago

    0 replies • 2300 views
  • Discussion

    Display Resource Editor: Different Colors for Schematic and Layout Axis

    Category: Custom IC Design

    By sgcad sgcad

    •

    updated 10 months ago by sgcad

    3 replies • 3327 views
  • Discussion

    Quantus not running an returning error with no description

    Category: Custom IC Design

    By Awab Awab

    •

    updated 10 months ago by ConradJ

    1 replies • 3377 views
  • Discussion

    How to get maximum value of s11 Trace

    Category: Custom IC Design

    By NS202408066722 NS202408066722

    •

    updated 10 months ago by NS202408066722

    2 replies • 2475 views
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