Custom IC Design

Latest Posts

Discussion

BUG: Drawing path in Virtuoso 6.1.6 only possible in routing layers

Category: Custom IC Design

By Sheppy

$usertype
•
updated over 9 years ago by ColinSutlieff

5 replies • 15329 views
Discussion

Post Layout Simulation Error

Category: Custom IC Design

By sdineshkumar

$usertype
•
updated over 9 years ago by Andrew Beckett

1 replies • 14052 views
Discussion

How to save current through inherited connections in a cell with AMS

Category: Custom IC Design

By twen

$usertype
•
updated over 9 years ago by twen

2 replies • 14976 views
Discussion

How to create dependent voltage source?

Category: Custom IC Design

By BaaB

$usertype
•
updated over 9 years ago by Andrew Beckett

9 replies • 23512 views
Discussion

Assura LVS error

Category: Custom IC Design

By jdgriggs

$usertype
•
updated over 9 years ago by bartman

6 replies • 17501 views
Discussion

Error during the traversal of the config myLib myCell config

Category: Custom IC Design

By twen

$usertype
•
updated over 9 years ago by twen

2 replies • 15107 views
Discussion

Reproduce monte-carlo results with changed netlist

Category: Custom IC Design

By Daniel S

$usertype
•
updated over 9 years ago by Daniel S

2 replies • 13853 views
Discussion

Pin snapping in VirtuosoXL

Category: Custom IC Design

By climbnc

$usertype
•
updated over 9 years ago by ColinSutlieff

1 replies • 14354 views
Discussion

Error found by spectre during circuit read-in--can't find process.scs library

Category: Custom IC Design

By jdgriggs

$usertype
•
updated over 9 years ago by ImanKian

24 replies • 22237 views
Discussion

layout migration

Category: Custom IC Design

By rafaelon

$usertype
•
updated over 9 years ago by ColinSutlieff

1 replies • 14890 views
Discussion

ERROR (SFE-23): "input.scs" 14: N0 is an instance of an undefined model nmos. Tried by adding simulator lang=spice in the first line of the model file

Category: Custom IC Design

By saikishore

$usertype
•
updated over 9 years ago by Andrew Beckett

3 replies • 6251 views
Discussion

Problem in calculation of Power dissipation

Category: Custom IC Design

By raghavendra ks

$usertype
•
updated over 9 years ago by Andrew Beckett

1 replies • 14043 views
Discussion

What's the difference between gate level extraction and transistor level extraction in Calibre xRC tool.

Category: Custom IC Design

By Biasing

$usertype
•
updated over 9 years ago by Biasing

2 replies • 11416 views
Discussion

How do you annotate region of operation for NMOS transistors in Cadence Virtuoso?

Category: Custom IC Design

By ocho

$usertype
•
updated over 9 years ago by Andrew Beckett

1 replies • 22995 views
Discussion

Assura LVS Error (Execution Terminated)

Category: Custom IC Design

By Sattar72

$usertype
•
updated over 9 years ago by Andrew Beckett

7 replies • 18223 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.