Custom IC Design

Latest Posts

Discussion

How to do advanced Analysis in ADE XL GUI

Category: Custom IC Design

By wgtkan

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 14849 views
Discussion

How to increase font size of plots axis labels & markers in Cadence virtuoso

Category: Custom IC Design

By venkmanbuster

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 6054 views
Discussion

plotting noise via Matlab

Category: Custom IC Design

By wgtkan

$usertype
•
updated over 6 years ago by wgtkan

3 replies • 15693 views
Discussion

noise/jitter transfer function along clock-driven inverter chain

Category: Custom IC Design

By nicodega

$usertype
•
updated over 6 years ago by Frank Wiedmann

13 replies • 20082 views
Discussion

Specifying Operating Region Expressions Using the Operating Region Assistant Pane in ADEXL

Category: Custom IC Design

By NorNand

$usertype
•
updated over 6 years ago by NorNand

1 replies • 15895 views
Discussion

pnoise jitter and pnoise time average discrepency: what is the problem?

Category: Custom IC Design

By skylink

$usertype
•
updated over 6 years ago by skylink

12 replies • 26735 views
Discussion

Call Python Function from Verilog A Device Model

Category: Custom IC Design

By cerealkiller

$usertype
•
updated over 6 years ago by Herge

1 replies • 15486 views
Discussion

phase noise/vin vs. frequency

Category: Custom IC Design

By skylink

$usertype
•
updated over 6 years ago by skylink

2 replies • 2156 views
Discussion

What is thermal noise called

Category: Custom IC Design

By wgtkan

$usertype
•
updated over 6 years ago by wgtkan

2 replies • 17044 views
Discussion

Reading from a file in Verilog-A

Category: Custom IC Design

By Manev

$usertype
•
updated over 6 years ago by Andrew Beckett

4 replies • 18577 views
Discussion

monte carlo simulation

Category: Custom IC Design

By Nathan Chen

$usertype
•
updated over 6 years ago by Frank Wiedmann

2 replies • 15639 views
Discussion

Question on ADE Assembler (maestro) corner setup

Category: Custom IC Design

By yizhu1

$usertype
•
updated over 6 years ago by yizhu1

4 replies • 17265 views
Discussion

Save VHDL variables of specific hierachy

Category: Custom IC Design

By michael10

$usertype
•
updated over 6 years ago by michael10

2 replies • 15041 views
Discussion

Libraries not imported in the Library manager

Category: Custom IC Design

By UUinfini

$usertype
•
updated over 6 years ago by UUinfini

8 replies • 19650 views
Discussion

Does MC mismatch simulation reflect best or arbitrary layout ?

Category: Custom IC Design

By HoWei

$usertype
•
updated over 6 years ago by HoWei

4 replies • 18085 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.