Custom IC Design

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Discussion

Layer Generation of Multiple Layers in Virtuoso

Category: Custom IC Design

By Tom Sawyer
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updated over 3 years ago by Andrew Beckett

10 replies • 14027 views
Discussion

clock buffer chain jitter measurement under deterministic supply noise

Category: Custom IC Design

By YutaoLiu
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updated over 3 years ago by FormerMember

7 replies • 13202 views
Discussion

Determine corner-dependent setting during operating point calculation with VerilogA model

Category: Custom IC Design

By FormerMember
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started over 3 years ago

0 replies • 3595 views
Discussion

Monte carlo simulation question

Category: Custom IC Design

By Holz
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updated over 3 years ago by Holz

2 replies • 9463 views
Discussion

how to plot THD against output voltage?

Category: Custom IC Design

By sahand1400
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updated over 3 years ago by FormerMember

7 replies • 12776 views
Discussion

Why there is no convergence in PSS and transient if I enable "Calculate initial conditions (ic) automatically"?

Category: Custom IC Design

By Clara Dong
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updated over 3 years ago by FormerMember

1 replies • 4165 views
Discussion

customize the CDL netlist

Category: Custom IC Design

By MReza123
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started over 3 years ago

0 replies • 10126 views
Discussion

Drawing in Layout XL

Category: Custom IC Design

By progster
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updated over 3 years ago by Marc Heise

1 replies • 9211 views
Discussion

Can I select simulation files via design variable? And can I sweep over a set of given parameters in ADE Assembler?

Category: Custom IC Design

By SteveVrk
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updated over 3 years ago by SteveVrk

2 replies • 10058 views
Discussion

Output expression has evaluation errors for corner sims

Category: Custom IC Design

By BillH314
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updated over 3 years ago by BillH314

4 replies • 12026 views
Discussion

veriloga output

Category: Custom IC Design

By greywanderer
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updated over 3 years ago by greywanderer

5 replies • 11803 views
Discussion

Function to add scs file to model libraries

Category: Custom IC Design

By dragank
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updated over 3 years ago by Andrew Beckett

6 replies • 12535 views
Discussion

How to use PSS+PSTB or PSS+PAC to simulation the loop gain of the amplifier in the MDAC in each clock phases

Category: Custom IC Design

By ringamplifier
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updated over 3 years ago by nraf

20 replies • 30295 views
Discussion

Parametric Simulation on number of fins

Category: Custom IC Design

By Legion
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updated over 3 years ago by Andrew Beckett

1 replies • 9816 views
Discussion

[liberate] unable to identify the device type for...

Category: Custom IC Design

By sherryshe
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updated over 3 years ago by sherryshe

2 replies • 10771 views

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