Custom IC Design

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Installscape/Cadence Installation Questions

Category: Custom IC Design

By growingmind

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updated over 6 years ago by Andrew Beckett

1 replies • 8669 views
Discussion

Difference in "Voltus_Power_Integrity_Fi_L" && "Virtuoso_Power_System_XL"

Category: Custom IC Design

By Amar Kumar

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updated over 6 years ago by Andrew Beckett

10 replies • 3357 views
Discussion

ADE XL Error

Category: Custom IC Design

By wgtkan

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updated over 6 years ago by wgtkan

2 replies • 17470 views
Discussion

Error when try to use ADE simulator to initialize

Category: Custom IC Design

By Ning08

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updated over 6 years ago by Andrew Beckett

3 replies • 17107 views
Discussion

Layout problem when trying to see layers

Category: Custom IC Design

By abdoboua

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updated over 6 years ago by Andrew Beckett

1 replies • 14104 views
Discussion

How can i enable annotations in virtuoso?

Category: Custom IC Design

By Genas

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updated over 6 years ago by Andrew Beckett

3 replies • 15490 views
Discussion

Annotation not working even after selecting the cdsparams

Category: Custom IC Design

By Genas

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updated over 6 years ago by Andrew Beckett

1 replies • 14810 views
Discussion

Creating a symbol view from the source code pointed by SimVision

Category: Custom IC Design

By RFStuff

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updated over 6 years ago by Andrew Beckett

1 replies • 13993 views
Discussion

Dynamic glitch check - on bus + variable level definition

Category: Custom IC Design

By sgserg

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updated over 6 years ago by Andrew Beckett

1 replies • 1255 views
Discussion

How to check the DC operating condition of a MOS in extracted netlist simulation

Category: Custom IC Design

By RFStuff

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updated over 6 years ago by Andrew Beckett

1 replies • 13971 views
Discussion

Virtuoso flatten verilog netlist generation question

Category: Custom IC Design

By Joonsoo

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updated over 6 years ago by Andrew Beckett

3 replies • 16475 views
Discussion

tie jitter function

Category: Custom IC Design

By Karev11

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updated over 6 years ago by Andrew Beckett

1 replies • 14676 views
Discussion

Full chip transistor level simulation convergence problem

Category: Custom IC Design

By Zhao Hui

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updated over 6 years ago by Andrew Beckett

1 replies • 14063 views
Discussion

Cadence crashes every time I change a wave's color

Category: Custom IC Design

By Kyle W

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updated over 6 years ago by Andrew Beckett

5 replies • 1952 views
Discussion

display result from on-going simulation

Category: Custom IC Design

By Karev11

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updated over 6 years ago by Karev11

2 replies • 14136 views

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