Custom IC Design

Latest Posts

Discussion

Run Options of ADE Assembler in Cadence Virtuoso

Category: Custom IC Design

By Senan
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updated over 3 years ago by Senan

6 replies • 13460 views
Discussion

Virtuoso License Issue: status code -5.

Category: Custom IC Design

By Paulo Aguirre
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updated over 3 years ago by Andrew Beckett

1 replies • 3552 views
Discussion

Maestro - Elapsed time to results

Category: Custom IC Design

By JeyJey
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updated over 3 years ago by FormerMember

11 replies • 5396 views
Discussion

illegal weak connection warning issue

Category: Custom IC Design

By Senan
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updated over 3 years ago by Andrew Beckett

1 replies • 12564 views
Discussion

question ： standard cell symbol import to virtuoso

Category: Custom IC Design

By jackkong
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updated over 3 years ago by jackkong

10 replies • 12916 views
Discussion

$analog_node_alias() usage with vector nets

Category: Custom IC Design

By dtodorov
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updated over 3 years ago by dtodorov

1 replies • 9221 views
Discussion

Exporting device component values and operating conditions into a table in Virtuoso

Category: Custom IC Design

By sidm
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updated over 3 years ago by FormerMember

3 replies • 10126 views
Discussion

constrain the memory use in cadence

Category: Custom IC Design

By huadel
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updated over 3 years ago by SC6789

3 replies • 16144 views
Discussion

Control flow when a return from an expression is nil

Category: Custom IC Design

By delgsy
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updated over 3 years ago by FormerMember

4 replies • 11129 views
Discussion

Any efficient way to do calibration using calcVal and MonteCarlo for tripple nested loop?

Category: Custom IC Design

By delgsy
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updated over 3 years ago by delgsy

2 replies • 9807 views
Discussion

DC Convergence Problem When Simulating a Post-Layout r_c and r_c_cc Extraction

Category: Custom IC Design

By shbmsra12
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updated over 3 years ago by Andrew Beckett

5 replies • 11737 views
Discussion

xi0.m1: Effective length is less than or equal to zero?? newbie in cadence!

Category: Custom IC Design

By archive
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updated over 3 years ago by Andrew Beckett

4 replies • 16445 views
Discussion

leaf cell issue with using diffstbprobe

Category: Custom IC Design

By kenc184
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updated over 3 years ago by kenc184

2 replies • 10545 views
Discussion

Saving the image of many output signals in Cadence Virtuoso

Category: Custom IC Design

By Senan
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updated over 3 years ago by Senan

2 replies • 10043 views
Discussion

Is it normal for DeCap to get 0 value leakage power when running liberate?

Category: Custom IC Design

By sherryshe
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updated over 3 years ago by Guangjun Cao

1 replies • 9420 views

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