Custom IC Design

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Discussion

ADE Model setup question

Category: Custom IC Design

By StephanWeber
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started over 2 years ago

0 replies • 5715 views
Discussion

Designing a Two stage CMOS OP Amp using Cadence Virtuoso_hspiceD simulator

Category: Custom IC Design

By Indhu Sekar
•
updated over 2 years ago by Andrew Beckett

11 replies • 14082 views
Discussion

Spice In with CDL netlist issue

Category: Custom IC Design

By AutoJeff
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started over 2 years ago

0 replies • 7789 views
Discussion

Calculation of noise multiplication factor (γ) for Ring VCO

Category: Custom IC Design

By Upendra Ch
•
updated over 2 years ago by Upendra Ch

5 replies • 7963 views
Discussion

Pin Creation Issue in Virtuoso Layout

Category: Custom IC Design

By POCHAMREDDY
•
updated over 2 years ago by RobMan

4 replies • 7769 views
Discussion

Download older version QUANTUS211

Category: Custom IC Design

By zhliang
•
updated over 2 years ago by mschw

1 replies • 6041 views
Discussion

Making Spiral Inductor Layout for EM simulations:

Category: Custom IC Design

By Upendra Ch
•
updated over 2 years ago by Upendra Ch

4 replies • 8035 views
Discussion

EVM Measurement (envlp analysis)

Category: Custom IC Design

By illaoi
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updated over 2 years ago by illaoi

3 replies • 7649 views
Discussion

Verilog-A: is it possible to nest analog events? e.g. timer() inside cross()?

Category: Custom IC Design

By dontpanic
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updated over 2 years ago by Andrew Beckett

1 replies • 9279 views
Discussion

Veriloga model of load behaves differently when standalone or instantiated with other circuit

Category: Custom IC Design

By unSkilled
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updated over 2 years ago by Andrew Beckett

2 replies • 6591 views
Discussion

Virtuoso ADE SKILL Reference ICADVM20.1: calcVal on a transient expression does not work

Category: Custom IC Design

By NewScreenName
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updated over 2 years ago by Andrew Beckett

1 replies • 6557 views
Discussion

About tsmc65 .proc file:

Category: Custom IC Design

By Upendra Ch
•
updated over 2 years ago by Andrew Beckett

1 replies • 8197 views
Discussion

VerilogA simulation error

Category: Custom IC Design

By TUKA
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updated over 2 years ago by TUKA

4 replies • 7070 views
Discussion

issue with assembler running corner simulations

Category: Custom IC Design

By greywanderer
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updated over 2 years ago by Andrew Beckett

1 replies • 5859 views
Discussion

How to derive edge phase noise from Output Noise in sampled Pnoise simulation

Category: Custom IC Design

By mxm14
•
updated over 2 years ago by Frank Wiedmann

11 replies • 14285 views

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