Custom IC Design

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Discussion

Which "efficient algorithm" uses ADE-XL for global optimization?

Category: Custom IC Design

By desyddd

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updated over 6 years ago by desyddd

2 replies • 3054 views
Discussion

How to do back annotation for wire RC extraction from layout to schematic

Category: Custom IC Design

By popoYoHo

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updated over 6 years ago by Andrew Beckett

3 replies • 15133 views
Discussion

Installscape/Cadence Installation Questions

Category: Custom IC Design

By growingmind

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updated over 6 years ago by Andrew Beckett

1 replies • 8048 views
Discussion

Difference in "Voltus_Power_Integrity_Fi_L" && "Virtuoso_Power_System_XL"

Category: Custom IC Design

By Amar Kumar

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updated over 6 years ago by Andrew Beckett

10 replies • 2904 views
Discussion

ADE XL Error

Category: Custom IC Design

By wgtkan

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updated over 6 years ago by wgtkan

2 replies • 16592 views
Discussion

Error when try to use ADE simulator to initialize

Category: Custom IC Design

By Ning08

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updated over 6 years ago by Andrew Beckett

3 replies • 16137 views
Discussion

Layout problem when trying to see layers

Category: Custom IC Design

By abdoboua

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updated over 6 years ago by Andrew Beckett

1 replies • 13396 views
Discussion

How can i enable annotations in virtuoso?

Category: Custom IC Design

By Genas

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updated over 6 years ago by Andrew Beckett

3 replies • 14623 views
Discussion

Annotation not working even after selecting the cdsparams

Category: Custom IC Design

By Genas

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updated over 6 years ago by Andrew Beckett

1 replies • 14094 views
Discussion

Creating a symbol view from the source code pointed by SimVision

Category: Custom IC Design

By RFStuff

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updated over 6 years ago by Andrew Beckett

1 replies • 13300 views
Discussion

Dynamic glitch check - on bus + variable level definition

Category: Custom IC Design

By sgserg

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updated over 6 years ago by Andrew Beckett

1 replies • 1054 views
Discussion

How to check the DC operating condition of a MOS in extracted netlist simulation

Category: Custom IC Design

By RFStuff

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updated over 6 years ago by Andrew Beckett

1 replies • 13308 views
Discussion

Virtuoso flatten verilog netlist generation question

Category: Custom IC Design

By Joonsoo

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updated over 6 years ago by Andrew Beckett

3 replies • 15554 views
Discussion

tie jitter function

Category: Custom IC Design

By Karev11

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updated over 6 years ago by Andrew Beckett

1 replies • 13942 views
Discussion

Full chip transistor level simulation convergence problem

Category: Custom IC Design

By Zhao Hui

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updated over 6 years ago by Andrew Beckett

1 replies • 13370 views

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