Encounter 8.1 vs 9.1 sdf generation

 If you could share what switches you are using for write_sdf, it would be helpful in pinpointing the problem.

Are you defining what views to use while writing sdf like -max_view, -typ_view, -min_view?

Hi diablo,

Here is what I do through the GUI, with a little more detail, (same for both versions).

1- Start encounter
2- Restore design from an encounter format
3- Do RC extract (simplest kind, not sign-off)
4- Calculate timing

It translates to the following commands in the log file, after loading the project:

Encounter 8.1: 
<CMD_INTERNAL> isExtractRCModeSignoff
<CMD> extractRC
<CMD> delayCal -sdf SPI_Demo_8.1.sdf -idealclock

Encounter 9.1:
<CMD> extractRC
Extraction called for design 'SPI_Demo' of instances=169 and nets=130 using extraction engine 'preRoute' .
<CMD> write_sdf -ideal_clock_network SPI_Demo_9.1.sdf

So no, it doesn't specify the views :(.  I looked in the command documentation and found the info on -max/min/typ_view and the -view switches. It looks like what I'm looking for, because the -view switch mentions it doesn't populate the typ slot. This is great news, but I have 3 other questions:

1- The commands require a "viewName" argument. What's this and how do I know what to give as argument? The documentation is not very detailed on this point.
2- The switches are said to be used in Multi Mode Multi Corner analysis, but I haven't done this yet (unless the Extract RC does this without telling me). I'm pretty sure it should be standard verification for sign-off, but for now I just want a quick'n dirty annotation file. Do I really have to do corner analysis at this point?
3- Can you set this option in the GUI? Everything will end up in a script, but it's always nice to have GUI handy.

Thanks

The first thing i noticed in sdf values between your 8.1 and 9.1 run is that their precision is different. 

 You can use write_sdf -prec to determine how much precision you want. If you want to compare 9.1 with 8.1, use write_sdf -prec 4 while writing sdf. 

Secondly, it didn't look like you were getting corners interconnect delay in your 8.1 run. Something is not right, if you were expecting corner delays there. In your 9.1, you are getting corner delays, and the one with 0's might be just becuase of precision.  

You have to create analysis view for MMMC analysis. But looks like your intent is to do just bcwc analysis.

You said you wanted sdf for back annotated simulation. While doing back annotated simulation, do you run in all three corners?

Hi diablo,

Thanks for the info.

Let me clear up my intent, it might help. Before starting on the real design layout, I'm doing a first run around the whole back-end process using a very small project to iron out any problems I might run into. It real project is mixed signal, with many small analog instances at the bottom of the hierarchy and the digital parts wrapping the top. I've worked through a basic assembly flow, and I am currently working on simulation with layout parasitics. I was hoping to look into MMMC and thermal/power analysis at a later time, because my test circuit seems a little too simple to have much self-training value for these features. Also, I don't think I can do full parasitics extraction directly in Encounter because of the custom analog blocs. However, I can produce DSPF or SPEF files for the digital portion of the mixed-signal design outside encounter, and import the result to calculate the delays.

When simulating, I don't remember giving a particular corner (or three. I use AMS for mixed signal), but I am currently aiming for a simple bcwc to start with. But if I can, I'd rather do it right on the first go so I won't have to come back and rework the procedure. From what I understand, you can only run one corner at a time, and let the hold/setup checks do the work of flagging errors for each corner setting. But then, for a simulation aiming to verify the mixed-signal circuit in typical conditions,  I'd need the typical values, so I would need to run MMMC right away?

Another question, to make sure : Should I expect problems when running MMMC with imported parasitics? I won't need to generate a SPEF file for each corner, right? The software will pick the right model when calculating the delays?

Am I thinking in the right direction?

Thanks

If i understood correctly, you want to do mixed signal timing simulation with parasitic delay included. When you do extraction of your top level to generate SPEF, you could generate spef_typical, spef_best, spef_wst for different corners. Then before writing out sdf, you could just use  "set_analysis_view -setup best -hold best","spefIn spef_best'(look in cmd ref for full syntax), and then write_sdf . This will give sdf with interconnect delay for you best corner. Do the same thing for all 3 corners with corresponding spef and view. Then finally you have to combine all the sdf using "sdfCombine" to generate single sdf file with all three corners delay values populated.

This may not be the most efficient way to do it. I will let other forum users to comment on the ways they are generating sdf.

Thanks a lot for the info, it helps me take a new look on the issue.

Cheers.

We made a switch in the Encounter platform from using SDF generated by the delayCal command
and that produced by the write_sdf command.  All new development on SDF will be using write_sdf - this
is different code that delayCal - and thus has some different - generally better behaviors.

In bcWc mode, the software is computing two corners worth of delays - best case and worst case. In OCV mode,
we are also computing delays twice for early vs. late delays.  The resulting SDF is just this:

     (bc::wc)  for bcWc mode  or (early::late) for OCV mode

A typ(ical) value is never computed, and so it is never written out.  Any value we would put there would strictly be
placeholder and would have no real meaning.  Leaving the typ SDF slot empty makes it clear to anyone looking at the SDF
that no real Typ corner delay calculation was done.

MMMC allows you to create more than a two corner delay environment - you can now really have bc, wc and typ
(and others) computed.  In this case, write_sdf now gives the option to specify how to populate the min:typ:max
SDF slots from the different views. 

- Ed

Hi Diablo and Martinage,

I had some time to come back to this problem, and found what I was looking for thanks to your help and pointers. Here is what I did:

The project comes with wcbc already setup, so I added a typical view in MMMC by following the user guide chapter on MMMC (this thread: http://www.cadence.com/Community/forums/p/11116/13162.aspx).

In the following lines, "default_mode_setup" and "default_mode_hold" already existed in  my project (bcwc), and point to the same .sdc file. "default_view_setup" and "default_view_hold" were also already defined.

create_library_set -name typical_libraries -timing {tt_1p5v_25c.lib} -si {tt_1v50_c25.cdB}
create_rc_corner -name typical_rc_corner -cap_table "typ.capTbl" -T -25 -qx_tech_file "typ.tch"                                                 
create_delay_corner -name typical_delay_corner -library_set typical_libraries -rc_corner typical_rc_corner
create_analysis_view -name typical_analysis_view -delay_corner typical_delay_corner -constraint_mode default_mode_setup

then:
set_analysis_view -setup {default_view_setup typical_analysis_view} -hold {default_view_hold typical_analysis_view}

and lastly
write_sdf -version 2.1 -typ_view typical_analysis_view -min_view default_view_hold -max_view default_view_setup test.sdf

I quickly checked an entry in the sdf file before and after these, and the early/late entries are unchanged, with new entries in the center field that make sense to me, so I think at worst I didn't break anything.

Again, thanks to both of you for your help.

Mz