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Cannot add TIEHI/TIELO cell successfully.

baixf
Hi, I ran the addTieHiLo command after placement, but no TIEH/TIEL cell was added. I found there were many net connecting with 1'b0 in the netlist, and I have run setTieHiLoMode -cell "TIEH TIEL" successfully. Can someone tell me what I should check for this problem? Thanks. Regards, Xuefei
  • wally1

    Make sure the functionality of the tie high/low cells are defined properly in the timing lib. See the following solution for more details:

    http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11021248

    Regards,

    Brian

  • baixf

    Thank you, Brian.

    I have checked the .lib file. The function of the TIEH and TIEL cells are defined correctly as described in the solution.

    Regards,

    Xuefei

     

  • baixf
    I find that, only 1'b0 and 1'b1 in the top-level module can be tied to TIEHI/TIELO cells correctly. How to solve this problem? Thanks. Regards, Xuefei
  • baixf
    I found the problem. The 1'b0 or 1'b1 which cannot be tied off correctly are unconnected ports of sub-modules. In Verilog netlist file, they are assigned to 1'b0, but in fact they do not exist in the layout. Xuefei

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