Digital Implementation

Latest Posts

Discussion

How to report the missing net in spef file

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

1 replies • 13319 views
Discussion

tip: to avoid xtalk on clock nets

Category: Digital Implementation

By archive
•
started over 18 years ago

0 replies • 12746 views
Discussion

Need contract PCB desiogn help

Category: Digital Implementation

By archive
•
started over 18 years ago

0 replies • 12515 views
Discussion

How to query row area of the block

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

2 replies • 14012 views
Discussion

output pin connected to power/ground net

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

1 replies • 1543 views
Discussion

Any way to report logic names of buffers/inverters ripped up during PlaceDesign?

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

1 replies • 902 views
Discussion

How to get the database address of the subModule?

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

4 replies • 14024 views
Discussion

Controlling logic names of CTS inserted buffers.

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

6 replies • 15750 views
Discussion

How to retrieve the variable which is defined in the SOC Encounter configure file ?

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

5 replies • 14082 views
Discussion

PVT corner for worst case power analysis

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

6 replies • 24618 views
Discussion

Cadence website low power page

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

1 replies • 12792 views
Discussion

Richard Goering's blog on CPF

Category: Digital Implementation

By archive
•
started over 18 years ago

0 replies • 422 views
Discussion

Low Power tip of the Week: Special cells fro advanced low power techniques

Category: Digital Implementation

By archive
•
started over 18 years ago

0 replies • 12761 views
Discussion

Low Power Tip of the Week: Power consumption on tester

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

1 replies • 13037 views
Discussion

How to make nanoroute understand "USEMINSPACING"

Category: Digital Implementation

By archive
•
updated over 18 years ago by archive

4 replies • 6517 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.