Digital Implementation

Latest Posts

Discussion

vsdlss Error in Encounter Power System

Category: Digital Implementation

By biju4u90

$usertype
•
started over 10 years ago

0 replies • 13218 views
Discussion

CCOpt-CTS

Category: Digital Implementation

By jij710

$usertype
•
started over 10 years ago

0 replies • 13655 views
Discussion

CCOpt-CTS

Category: Digital Implementation

By jij710

$usertype
•
updated over 10 years ago by jij710

2 replies • 17710 views
Discussion

Intrinsic Delay

Category: Digital Implementation

By jij710

$usertype
•
updated over 10 years ago by kenambo

1 replies • 14355 views
Discussion

Error in early rail analysis in Cadence EPS

Category: Digital Implementation

By biju4u90

$usertype
•
started over 10 years ago

0 replies • 13461 views
Discussion

Endpoint margins

Category: Digital Implementation

By Vikk

$usertype
•
started over 10 years ago

0 replies • 13211 views
Discussion

Find net name in Encounter with dbGeet

Category: Digital Implementation

By gdellaca

$usertype
•
updated over 10 years ago by gdellaca

4 replies • 16424 views
Discussion

Clock Mesh specification in Encounter: analysis specification

Category: Digital Implementation

By HansRey

$usertype
•
started over 10 years ago

0 replies • 13366 views
Discussion

looking for documents relating to noise analysis in EDI

Category: Digital Implementation

By chris06

$usertype
•
started over 10 years ago

0 replies • 13332 views
Discussion

Clock definition in sdc file

Category: Digital Implementation

By gdellaca

$usertype
•
started over 10 years ago

0 replies • 15879 views
Discussion

MACRO TO MACRO CHANNEL

Category: Digital Implementation

By jij710

$usertype
•
started over 10 years ago

0 replies • 15549 views
Discussion

BUFFER/INVERTER COUNT AFTER CTS

Category: Digital Implementation

By jij710

$usertype
•
updated over 10 years ago by admin

3 replies • 2306 views
Discussion

ELC Simulation failed with status 512

Category: Digital Implementation

By rangha

$usertype
•
updated over 10 years ago by jsaenznoval

4 replies • 15139 views
Discussion

Max Tran and max cap violations on tristate nets

Category: Digital Implementation

By bitmaster

$usertype
•
started over 10 years ago

0 replies • 15461 views
Discussion

Verilog netlist import not creating a schematic view for some modules.

Category: Digital Implementation

By cjpatil2

$usertype
•
started over 10 years ago

0 replies • 14690 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.