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Digital Implementation

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  • Discussion

    addRing creating rings outside design boundary

    Category: Digital Implementation

    By TA202503121730

    •

    started over 1 year ago

    0 replies • 3678 views
  • Discussion

    gsclib045 data sheet available?

    Category: Digital Implementation

    By FG202508072745

    •

    started over 1 year ago

    0 replies • 3202 views
  • Discussion

    Issue about using SkyWater130 and Genus

    Category: Digital Implementation

    By SR202412023415

    •

    started over 1 year ago

    0 replies • 3438 views
  • Discussion

    Residual power in whole design vs summed gate groups in Joules, even with full instance coverage

    Category: Digital Implementation

    By SR202412023415

    •

    started over 1 year ago

    0 replies • 3373 views
  • Discussion

    DRC Violations due to Macro Placement and Power Straps in Innovus Stylus Flow

    Category: Digital Implementation

    By XL202501136611

    •

    started over 1 year ago

    0 replies • 5298 views
  • Discussion

    How to manage block-level and top-level SDC constraints?

    Category: Digital Implementation

    By MichR

    •

    started over 1 year ago

    0 replies • 5354 views
  • Discussion

    Min Pulse Width Violation

    Category: Digital Implementation

    By SG20250716916

    •

    started over 1 year ago

    0 replies • 3220 views
  • Discussion

    Congestion at Routing Stage

    Category: Digital Implementation

    By SG20250716916

    •

    started over 1 year ago

    0 replies • 3276 views
  • Discussion

    Foundation flow stylus

    Category: Digital Implementation

    By VK20250620161

    •

    started over 1 year ago

    0 replies • 3290 views
  • Discussion

    INNOVUS: connect internal power nets between hard macros

    Category: Digital Implementation

    By PK202501238151

    •

    started over 1 year ago

    0 replies • 4193 views
  • Discussion

    Tracing Gates to RTL Modules and Line Numbers in Flattened Netlist with Genus

    Category: Digital Implementation

    By SR202412023415

    •

    started over 1 year ago

    0 replies • 3697 views
  • Discussion

    Synthesizing Specific Gates in Cadence Genus

    Category: Digital Implementation

    By SR202412023415

    •

    updated over 1 year ago by SR202412023415

    2 replies • 6834 views
  • Discussion

    Cadence Genus: Submodule synthesis and reuse and integrate it in top module

    Category: Digital Implementation

    By XH202505277146

    •

    started over 1 year ago

    0 replies • 4557 views
  • Discussion

    in VSVN netlist getting error , i am using mlcv swicth

    Category: Digital Implementation

    By SM20250402327

    •

    updated over 1 year ago by SM20250402327

    1 replies • 3806 views
  • Discussion

    Glitch in Synthesized Netlist Simulation of SR Latch — Occurs Only in One Instance

    Category: Digital Implementation

    By SaranyaBalan

    •

    started over 1 year ago

    0 replies • 4194 views
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