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  3. Code coverage for sv verification envrionment

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Code coverage for sv verification envrionment

Jeff000
Jeff000 over 7 years ago

I referred to the link below but it seems it is much a historical solution. Now I am trying on IES 15.023. So is it possible to generate code coverage for sv verification environment with irun?

Thanks.

https://community.cadence.com/cadence_technology_forums/f/functional-verification/9140/generating-code-coverage-for-sv-verification-environment

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  • StephenH
    StephenH over 7 years ago

    Yes, the answer remains the same: if you have a module-based testbench you can use "-coverage all" to enable all types of coverage and it will include the testbench modules. If you want coverage of a class-based testbench, you'll need to use the "-covfile" switch and pass some specific options, please refer to the "select_coverage" CCF command in this documentation page:  Coverage Control File options

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  • tpylant
    tpylant over 7 years ago

    You can enable with CCF command:

      select_coverage –b –class          

    Options are available to selectively enable coverage inside certain classes.

    • To De-select UVM package

                deselect_coverage   -b -class -module uvm_pkg

    • To deselect `UVM macros one could add to CCF

                deselect_macro        -class -name UVM*  uvm*

    The would help to reduce unwanted coverage due to standardized macros and standardized library functions.

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