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Code coverage for sv verification envrionment

Jeff000

I referred to the link below but it seems it is much a historical solution. Now I am trying on IES 15.023. So is it possible to generate code coverage for sv verification environment with irun?

Thanks.

https://community.cadence.com/cadence_technology_forums/f/functional-verification/9140/generating-code-coverage-for-sv-verification-environment

Parents

  • Yes, the answer remains the same: if you have a module-based testbench you can use "-coverage all" to enable all types of coverage and it will include the testbench modules. If you want coverage of a class-based testbench, you'll need to use the "-covfile" switch and pass some specific options, please refer to the "select_coverage" CCF command in this documentation page:  Coverage Control File options

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  • Yes, the answer remains the same: if you have a module-based testbench you can use "-coverage all" to enable all types of coverage and it will include the testbench modules. If you want coverage of a class-based testbench, you'll need to use the "-covfile" switch and pass some specific options, please refer to the "select_coverage" CCF command in this documentation page:  Coverage Control File options

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