Functional Verification

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Discussion

SystemVerilog "interface class"

Category: Functional Verification

By ChasL

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updated over 8 years ago by Tudor Timi

1 replies • 1923 views
Discussion

Issue related to use of cadence analog fetch function $cgav with a multi-bit analog signal

Category: Functional Verification

By bhanu27

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started over 8 years ago

0 replies • 15157 views
Discussion

Analog value fetch functions : issue with incisiv 15.20.004

Category: Functional Verification

By bhanu27

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updated over 8 years ago by bhanu27

4 replies • 16434 views
Discussion

How to suppress the prefix of path when launch imc?

Category: Functional Verification

By Jeff000

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updated over 8 years ago by Jeff000

1 replies • 1184 views
Discussion

[ncsim: *W,DLWNEW:] How to locate the intermediate file?

Category: Functional Verification

By Jeff000

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updated over 8 years ago by tpylant

1 replies • 3780 views
Discussion

[PROBLEM_STRING FAILED] What could be the causes for this error message?

Category: Functional Verification

By Jeff000

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updated over 8 years ago by TAM1

1 replies • 1222 views
Discussion

Compilation Errors for UVM constructs using xcelium

Category: Functional Verification

By Iovi

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started over 8 years ago

0 replies • 15927 views
Discussion

What if inheritance occurs for a class with an embedded covergroup?

Category: Functional Verification

By Jeff000

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updated over 8 years ago by TAM1

3 replies • 3906 views
Discussion

IMC Code Coverage : vRefine for reading waivers.

Category: Functional Verification

By Saru K S

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started over 8 years ago

0 replies • 16755 views
Discussion

Lost bins in coverpoint?

Category: Functional Verification

By Jeff000

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started over 8 years ago

0 replies • 648 views
Discussion

Embedded cover group got started automatically?

Category: Functional Verification

By Jeff000

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started over 8 years ago

0 replies • 528 views
Discussion

lib.map load order anomaly

Category: Functional Verification

By SysTom

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started over 8 years ago

0 replies • 13518 views
Discussion

*E,SOSSZI Slice size for streaming concatenation expression has an illegal value

Category: Functional Verification

By Jeff000

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updated over 8 years ago by Jeff000

1 replies • 981 views
Discussion

How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?

Category: Functional Verification

By iguerra

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started over 8 years ago

0 replies • 380 views
Discussion

Display signals in Simvision

Category: Functional Verification

By mjtorrie68

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updated over 8 years ago by Doug Koslow

2 replies • 22481 views

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