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Functional Verification

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    Search Path and Packages, Interface, etc.

    Category: Functional Verification

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    updated over 18 years ago by archive

    4 replies • 15819 views
  • Discussion

    HD Audio eVC/uVC

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 446 views
  • Discussion

    IPCM question?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 14807 views
  • Discussion

    Can I force or probe a signal in vhdl module from verilog top testbench?

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 18499 views
  • Discussion

    How to tackle 'Aborted' properties.

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 6360 views
  • Discussion

    How frequently should Transactor work?

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 14152 views
  • Discussion

    Internal IUS error

    Category: Functional Verification

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    updated over 18 years ago by archive

    7 replies • 17514 views
  • Discussion

    How to probe and view the variable wave in class?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 20985 views
  • Discussion

    parsing the arguments from command line

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 20987 views
  • Discussion

    Come see the URM in action on May 2

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 13248 views
  • Discussion

    Passing e defines through Model Sim

    Category: Functional Verification

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    updated over 18 years ago by archive

    2 replies • 14523 views
  • Discussion

    About URM library

    Category: Functional Verification

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    updated over 18 years ago by archive

    2 replies • 14132 views
  • Discussion

    C++ code through DPI?

    Category: Functional Verification

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    updated over 18 years ago by archive

    2 replies • 16272 views
  • Discussion

    SC-SV-Verilog interface

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 13371 views
  • Discussion

    SC and SV co-simulation in IUS?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 15127 views
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