Functional Verification

Latest Posts

Discussion

Simulation time increase?

Category: Functional Verification

By Sparsh Gupta

$usertype
•
updated over 6 years ago by Tudor Timi

2 replies • 15820 views
Discussion

regression/coverage collection/analyze flow

Category: Functional Verification

By yxpe

$usertype
•
updated over 6 years ago by yxpe

4 replies • 4201 views
Discussion

Export signal loads list

Category: Functional Verification

By gavinhtao

$usertype
•
started over 6 years ago

0 replies • 13822 views
Discussion

Disable VHDL assert using xrun

Category: Functional Verification

By NabilE

$usertype
•
updated over 6 years ago by NabilE

2 replies • 19557 views
Discussion

ncsim: Error within protected source code.

Category: Functional Verification

By DylanC

$usertype
•
updated over 6 years ago by joe321

8 replies • 25540 views
Discussion

Combining coverpoints

Category: Functional Verification

By Sparsh Gupta

$usertype
•
started over 6 years ago

0 replies • 14140 views
Discussion

ncvlog: *E,DLCIRD

Category: Functional Verification

By reddy9876

$usertype
•
updated over 6 years ago by hannes

1 replies • 2156 views
Discussion

IMC exclude conditionally

Category: Functional Verification

By Sparsh Gupta

$usertype
•
started over 6 years ago

0 replies • 14669 views
Discussion

Need help: *E,ILLPDL Error while compiling RTL design file which has typedef definition

Category: Functional Verification

By mahee424

$usertype
•
updated over 6 years ago by mahee424

6 replies • 6856 views
Discussion

How to use the "set_refinement_resilience" settings after design files are updated.

Category: Functional Verification

By prkroon

$usertype
•
updated over 6 years ago by prkroon

6 replies • 9686 views
Discussion

Elaboration Error ICDPAV on xcelium

Category: Functional Verification

By BrcmHarish

$usertype
•
updated over 6 years ago by StephenH

5 replies • 24539 views
Discussion

How to reinvoke a simulation by changing some testbench code in Simvision?

Category: Functional Verification

By Saru K S

$usertype
•
updated over 6 years ago by StephenH

1 replies • 19906 views
Discussion

XceliumMain_18.09 config error after install??

Category: Functional Verification

By RobMorin

$usertype
•
updated over 7 years ago by RobMorin

6 replies • 18384 views
Discussion

While debugging systemverilog@incisive, how do I print "this"?

Category: Functional Verification

By Avidan

$usertype
•
updated over 7 years ago by StephenH

3 replies • 3141 views
Discussion

How to print value of a systemverilog class instance when a breakpoint is hit?

Category: Functional Verification

By Avidan

$usertype
•
updated over 7 years ago by Avidan

5 replies • 18037 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.