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Functional Verification

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  • Discussion

    UVM Adapter for Pipelined protocols like AHB, AXI etc

    Category: Functional Verification

    By VeeJ

    •

    started over 2 years ago

    0 replies • 7407 views
  • Discussion

    how to force the variables inside a class? i'm facing this error "FOAUTO"

    Category: Functional Verification

    By chetan somana

    •

    updated over 2 years ago by chetan somana

    6 replies • 5763 views
  • Discussion

    Tagging uvm_errors in waveform file for post-processing

    Category: Functional Verification

    By antmarzam

    •

    updated over 2 years ago by Doug Koslow

    3 replies • 7537 views
  • Discussion

    verification metrics on IMC

    Category: Functional Verification

    By Nir Z

    •

    updated over 2 years ago by StephenH

    8 replies • 12173 views
  • Discussion

    $display() is executed immediately after simulation start although the condition in always statement (under which $display() resides) is not satisfied

    Category: Functional Verification

    By alexek

    •

    updated over 2 years ago by alexek

    1 replies • 6431 views
  • Discussion

    simvision failed to load the svwf waveform file "Error: bad condition name "duty1_reg_19_0__signmag_19_0_15"

    Category: Functional Verification

    By wangyunxin

    •

    started over 2 years ago

    0 replies • 1845 views
  • Discussion

    change text editor colors (not trace colors) used in Probe

    Category: Functional Verification

    By kspahr

    •

    updated over 2 years ago by tpylant

    1 replies • 6855 views
  • Discussion

    How to invoke the Xcelium Design Browser from Command Line?

    Category: Functional Verification

    By amnldm

    •

    updated over 2 years ago by StephenH

    5 replies • 16123 views
  • Discussion

    Stuck at a package not bound error in the accelerated UVM course

    Category: Functional Verification

    By arjunchak

    •

    updated over 2 years ago by tpylant

    1 replies • 9892 views
  • Discussion

    When running upf simulation power net is stuck at 0

    Category: Functional Verification

    By 2tojohny

    •

    updated over 2 years ago by richardcromwell

    1 replies • 8616 views
  • Discussion

    SimVision does not display a part of the signal plot

    Category: Functional Verification

    By WaliAshu

    •

    updated over 2 years ago by Doug Koslow

    3 replies • 9894 views
  • Discussion

    fixed-point in simvision

    Category: Functional Verification

    By wangyunxin

    •

    updated over 2 years ago by StephenH

    4 replies • 9623 views
  • Discussion

    SystemVerilog count the $error() output during simulation

    Category: Functional Verification

    By HoWei

    •

    updated over 2 years ago by StephenH

    1 replies • 10627 views
  • Discussion

    preprocessor directive

    Category: Functional Verification

    By daivon

    •

    updated over 2 years ago by StephenH

    1 replies • 6856 views
  • Discussion

    SIMVISION source browser- PPESNAP error

    Category: Functional Verification

    By sthoppa

    •

    updated over 2 years ago by sthoppa

    6 replies • 5219 views
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