Hardware/Software Co-Development, Verification and Integration

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Discussion

layout XL annoyance

Category: Hardware/Software Co-Development, Verification and Integration

By alpine

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started over 11 years ago

0 replies • 13328 views
Discussion

RMS jitter from eye diagram

Category: Hardware/Software Co-Development, Verification and Integration

By 34892

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started over 11 years ago

0 replies • 14111 views
Discussion

ViVA bus plot to full view plot

Category: Hardware/Software Co-Development, Verification and Integration

By 34892

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started over 11 years ago

0 replies • 13611 views
Discussion

Phantom Stage Problem (Pspice Design)

Category: Hardware/Software Co-Development, Verification and Integration

By Daniel P

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started over 11 years ago

0 replies • 13532 views
Discussion

Checking USB2 PHY via BIST

Category: Hardware/Software Co-Development, Verification and Integration

By Chronnos

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started over 11 years ago

0 replies • 13638 views
Discussion

CRT Flyback Transformer (LOPT) Simulation Model???

Category: Hardware/Software Co-Development, Verification and Integration

By Vignesh m93

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updated over 11 years ago by Alok Tripathi

1 replies • 15277 views
Discussion

cadence ifv tool:underlying verification methodology

Category: Hardware/Software Co-Development, Verification and Integration

By puchalapalli

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started over 11 years ago

0 replies • 726 views
Discussion

Pspice: keep plot settings

Category: Hardware/Software Co-Development, Verification and Integration

By FD00

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started over 11 years ago

0 replies • 14208 views
Discussion

Total capacitance

Category: Hardware/Software Co-Development, Verification and Integration

By gdallas

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updated over 11 years ago by gdallas

2 replies • 14474 views
Discussion

verilog testbench simulation

Category: Hardware/Software Co-Development, Verification and Integration

By sebgimi

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started over 11 years ago

0 replies • 14853 views
Discussion

how to add a stochastic noise to vsource

Category: Hardware/Software Co-Development, Verification and Integration

By smalldragon

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started over 11 years ago

0 replies • 13515 views
Discussion

veriloga spectre error

Category: Hardware/Software Co-Development, Verification and Integration

By Manikanta123

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updated over 11 years ago by Manikanta123

1 replies • 14608 views
Discussion

Generate spectre netlist from command line/script

Category: Hardware/Software Co-Development, Verification and Integration

By coco009

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updated over 12 years ago by crazysarik

7 replies • 8642 views
Discussion

signal order in simvision

Category: Hardware/Software Co-Development, Verification and Integration

By spark

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updated over 12 years ago by Doug Koslow

7 replies • 18301 views
Discussion

No Pspice template issue

Category: Hardware/Software Co-Development, Verification and Integration

By tt543

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updated over 12 years ago by fursys

10 replies • 22028 views

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