Logic Design

Latest Posts

Discussion

Design entry hdl

Category: Logic Design

By Danil3402
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updated over 10 years ago by grasshopper

1 replies • 5431 views
Discussion

Digital library for RTL compiler

Category: Logic Design

By mhkvy4
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updated over 10 years ago by grasshopper

2 replies • 13590 views
Discussion

RTL compiler error

Category: Logic Design

By Jinesh K B
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updated over 10 years ago by grasshopper

1 replies • 13596 views
Discussion

Using RC to estimate leakage & dynamic power from different synthesis runs

Category: Logic Design

By kenearth
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updated over 10 years ago by uma1147

1 replies • 1245 views
Discussion

How to compare 2 design entry HDL schematic?

Category: Logic Design

By maberu
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updated over 10 years ago by grasshopper

1 replies • 13810 views
Discussion

conformal lec : dump mapped points

Category: Logic Design

By HariPV
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started over 10 years ago

0 replies • 13594 views
Discussion

RC response[TUI-39]after "report clock_gating"

Category: Logic Design

By cwwang
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updated over 10 years ago by cwwang

2 replies • 1287 views
Discussion

Using multiple libraries - mixed elaboration flow

Category: Logic Design

By drovak
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started over 10 years ago

0 replies • 1720 views
Discussion

Mining information from RTL Compiler log file.

Category: Logic Design

By sgauria
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started over 10 years ago

0 replies • 12907 views
Discussion

How to perform dynamic power analysis using RTL compiler

Category: Logic Design

By marten
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updated over 11 years ago by grasshopper

1 replies • 13630 views
Discussion

LEC debug points report generation ???

Category: Logic Design

By aperla
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updated over 11 years ago by sogold

2 replies • 15994 views
Discussion

LEC - Conformal RTL to netlist mismatch

Category: Logic Design

By hnfq
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updated over 11 years ago by grasshopper

11 replies • 14188 views
Discussion

what is the Purpose of initial_target attribute of a cost group?

Category: Logic Design

By anudeep
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started over 11 years ago

0 replies • 12762 views
Discussion

LEC mismatch b/w RTL and Lec-Friendly netlist

Category: Logic Design

By anudeep
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started over 11 years ago

0 replies • 826 views
Discussion

how to synthesize delay elements in RTL complier

Category: Logic Design

By micro469
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updated over 11 years ago by grasshopper

3 replies • 15529 views

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