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Logic Design

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  • Discussion

    Conformal CEC checking

    Category: Logic Design

    By Sameerpy Sameerpy

    •

    updated over 1 year ago by Fotios Nt

    1 replies • 5324 views
  • Discussion

    how to tell conformal to ignore certain combination of input

    Category: Logic Design

    By gperry gperry

    •

    updated over 1 year ago by Fotios Nt

    1 replies • 4592 views
  • Discussion

    Error orprobe3086

    Category: Logic Design

    By elirazo elirazo

    •

    started over 1 year ago

    0 replies • 4104 views
  • Discussion

    Regarding the loading of waveform signals in the waveform windown using the tcl command

    Category: Logic Design

    By rahulkumarKKrahul rahulkumarKKrahul

    •

    updated over 1 year ago by rahulkumarKKrahul

    1 replies • 4988 views
  • Discussion

    Merge several worklibs

    Category: Logic Design

    By zzzzzzx zzzzzzx

    •

    started over 1 year ago

    0 replies • 4221 views
  • Discussion

    copy paste circuit from one schematic design to another

    Category: Logic Design

    By andyStubbs andyStubbs

    •

    started over 1 year ago

    0 replies • 5026 views
  • Discussion

    How to generate "Sheet Name" column in a pin report?

    Category: Logic Design

    By Gan Gan

    •

    updated over 1 year ago by Gan

    2 replies • 2004 views
  • Discussion

    How to identify old Orcad Schematic entry version

    Category: Logic Design

    By pautax pautax

    •

    updated over 1 year ago by pautax

    1 replies • 5044 views
  • Discussion

    Unable to open 64bit version of simvison

    Category: Logic Design

    By sthoppa sthoppa

    •

    updated over 1 year ago by sthoppa

    1 replies • 6050 views
  • Discussion

    Detailed waveform dumping for selected waveform

    Category: Logic Design

    By AndyWangsh AndyWangsh

    •

    started over 2 years ago

    0 replies • 7211 views
  • Discussion

    Conformal LEC can't finish at analyze abort step. How do I proceed?

    Category: Logic Design

    By mxlusereight mxlusereight

    •

    started over 2 years ago

    0 replies • 2872 views
  • Discussion

    DRC Developers question

    Category: Logic Design

    By MollyMeow MollyMeow

    •

    started over 2 years ago

    0 replies • 5478 views
  • Discussion

    Request information on Tools

    Category: Logic Design

    By DEEPACDAC DEEPACDAC

    •

    started over 2 years ago

    0 replies • 5322 views
  • Discussion

    Genus: Generated netlist doesn't define subckts

    Category: Logic Design

    By Anas2023a95 Anas2023a95

    •

    updated over 2 years ago by DimoM

    1 replies • 3314 views
  • Discussion

    Stream in gds to virtuoso from directory other than where cds.lib exists

    Category: Logic Design

    By polymorpher polymorpher

    •

    updated over 2 years ago by DimoM

    1 replies • 6859 views
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