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overlap error

Charanraj Mohan

Hi,

can someone suggest a way to avoid overlap error in a simple schematic. Say, I am simply connecting a capacitor at the end of an inverter and I get ' I0 and C0 overlap by more than 10 percent', when I do check and save. How to avoid this kind of error ??

thanks in advance.

  • Generally it should be a warning not an error unless your environment has been customised. First check that your inverter symbol actually has an instance box (this is the typically red line around the substantial part of the symbol when you open the symbol itself in the symbol editor, and can be created using Create->Selection Box). 

    However, if you are directly placing the capacitor on the output pin of the inverter with no wire in the way, then you'll almost certainly be actually overlapping the instance boxes. You can control the severity of this check (and how much overlap is tolerated) by going to Check->Rules Setup. Pick the "Physical" tab and then you can set whether overlapping instances trigger a warning or an error or are ignored, or you can increase the percentage (in my case increasing from 10 to 30% stopped a capacitor on the output of my inverter triggering a warning).

    Regards,

    Andrew.

  • BTW, having the check is quite a good idea - because I've seen cases where people have accidentally placed multiple instances on top of each other and then didn't notice that actually they had several in parallel.

  • Got it! I should take care that, the components do not overlap on the selection box of a symbol. As I have deleted the selection box to make the schematic look better, I couldn't find it. Now, I have corrected and will take care of such hereafter. Thanks Andrew :-)

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