how to convert text string to integer in VerilogA?

Hi David,

Which manual are you looking at? I just looked at the Cadence® Verilog®-A Language Reference manual from SPECTRE17.1 and there is no mentioned of "reg" there. I'd be surprised because it's a digital construct and so makes no sense in the analog Verilog-A language. If it was the Cadence® Verilog®-AMS Language Reference manual from an INCISIVE or XCELIUM stream (may be in the IC stream too - I forget) then that would make more sense, but then it would be talking about Verilog AMS and you'd have to use a Verilog AMS view and simulate it in AMS Designer.

Regards,

Andrew.

Hi Andrew,

very funny. we are looking up from Verilog-AMS for Verilog-A! 

by all means, how can I convert text string (like "Hello World") into ASCII value (so that I can wiggle a vector variable for plotting purpose)? 

thanks,

David

hi Andrew,

one more thing regarding "reg" in VerilogAMS. I create VerilogAMS view from IC617, using the exact example as from AMS LRM, but the Text Editor still complains " `reg' is not a reserved keyword now but will be one in a future release." when I click "Check and Save". 

     reg [8*12:1] stringvar ;

     initial begin
          stringvar = "Hello world!" ;
     end

you sure "reg" is supported in VerilogAMS? 

I just like the way for easy string bit(s) access.

thanks,

David

Hi David,

This is for the same reason as your other post. You've not created a VerilogAMS view, but a VerilogA view which has a view name of "verilogams". That's not the same thing.

I just tried this in a VerilogAMS view type (i.e. choice of type "VerilogAMSText" in the File->New form) and it works OK. You can tell because the messages you were getting above are coming from spectre, which is used as the language parser when you're using VerilogA, but if you use VerilogAMS it's using INCISIVE/XCELIUM instead.

Regards,

Andrew.

yup, you are right. I made a shortcut. I got this work now. but unfortunately the tool still limiting me changing such "reg" varibles being changed inside "analog" block. anyway, I worked around. 

thanks,

David

just following up my side, I kind give up to let VerilogA convert text into ascii. I just give the ascii value directly. 

here's the ascii display I get from VerilogA code in ViVa, 

That's because reg are digital, and so can only be changed in a digital block (i.e. outside of an analog block). That's expected and how the language works.

Andrew.

yup, I guess that's the way it meant to be. 

one more question will we are still on this, I see from ViVa, I can have digital bus in radix of Binary, Hex, ..., Ascii. but when I create bus by awvCreateBus in Ocean, seems it doesn't support radix of "Ascii". Is it possible to create the bus in "Ascii" radix so I don't have to click every time a new waveform plotted?

to further clarify what I'm seeing, regardless what radix I give to awvCreateBus, e.g., Binary or Ascii, the plot command always give "Hex" display. I have to manually change the Radix from ViVa. looks like plot command dropped radix info? better command I can use?

  comment_bus = awvCreateBus("comment_bus" list( ... ) "Ascii")

   plot( comment_bus ?expr '( "COMMENT" ) )

thanks,

David

David,

It works for me. Which IC subversion are you using?

Regards,

Andrew.

Hi Andrew, that's awesome if working there. 06.17.709