Format of "VCD Info File"

Well ... I've found a description in Appendix E of Spectre® Circuit Simulator and Accelerated Parallel Simulator User Guide

and created vcd_info file according to the this document.

Here is the content of the vcd_info :

.voh 5.0

.vol 0.0

.scope simple_clock(bhv)

.out clock

where simple_clock(bhv) - the name of digital block entity(architecture) from which I creaed vcd.

clock - the only output from the block.

At the Virtupso side the schematic is very simple: only one component - resistor, connected to GND at one side, at other - to the floating net named "clock".

When I run Spectre, I get the following:

Notice from spectre during topology check.
Only one connection to the following 2 nodes:
0
clock
Error found by spectre during initial setup.
ERROR (USIMPRS-17866): No Data read from the vcd file, please verify that the scopes are correct and there are in and/or out vectors specified.
Fatal error found by spectre during initial setup.
FATAL (SPECTRE-13004):

When trying the setup from previous message, I erroneously worked with wrong file.

Here is setup that simulates, but still there is no connection between stimuli signal and node in Virtuoso schematic.

The top of .vcd file:

$comment
TOOL: simvision(64) 12.10-s019
$end

$date
Jul 01, 2019 15:18:55
$end

$timescale
1fs
$end

$scope module simple_clock $end
$var wire 1 ! clock1 $end
$upscope $end

$enddefinitions $end
#0
$dumpvars
0!
$end
#50000000
1!
#100000000
0!
#150000000
1!
#200000000

..........

The content of vcd_info:

.hier 1
.voh 5.0
.vol 0.0

.scope simple_clock
.out clock1

Note from simulation log:

Only one connection to the following 2 nodes:

0

clock1

As result - the clock1 is kept to 0.

Any comments.

Thanks

Well, actually I don't understand what really happens ... I modify the content of the vcd_info and .vcd (e.g. change the name of signal) and rerun simulation, but simulator always shows the same message as if it dodn't see modifications.

So after each modification should I close and reopen ADE ?

Hit the stop button in ADE. Normally ADE (L) keeps spectre running and most likely it's not refreshing if the contents change.

It does work with .in. If I use this:

.hier 1
.vih 5.0
.vil 0.0

.scope simple_clock
.in clock1

Then I get a signal called simple_clock.clock1 - i.e. a signal inside the hierarchical instance called simple_clock (which gets created if it doesn't exist in your design).You should also use vih/vil rather than voh/vol. It's not going to drive a top level signal called clock1. If you wanted that, you need to use .hier 0 instead. Or add:

.alias simple_clock.clock1 clock1

The checking of output vectors does indeed work with spectre (I just checked) - I get a file called input_tran.vecerr with the details of any mismatch between the signals marked as outputs and the actual signals in the simulation - so it's to check that the response is what you expect.

For more details, look at the Rapid Adoption Kit Using VEC and VCD files in AMS and Analog Simulation in ADE

Regards,

Andrew.

Yes !!!

Thanks Andrew !

Andrew,

When I try with real testbench the problem reappears.

Here is definition section of .vcd:

$scope module tb_top $end

$scope module inst_as2005_left $end

$scope module ANA $end
$var wire 1 ! afe_pd $end
$var wire 8 " cal_dac [7:0] $end
$var wire 1 # cal_load $end
$var wire 1 $ cal_on $end
$var wire 1 % cal_readout $end
$var wire 3 & cap [2:0] $end
$var wire 3 ' comp1 [2:0] $end
$var wire 3 ( comp2 [2:0] $end
$var wire 51 ) grp1_adc [50:0] $end
$var wire 1 * grp1_blo_on $end
$var wire 1 + grp1_cds1 $end
$var wire 1 , grp1_cds2 $end
$var wire 1 - grp1_clk $end
$var wire 1 . grp1_irst $end
$var wire 1 / grp1_lpf_on $end
$var wire 1 0 grp1_s1 $end
$var wire 1 1 grp1_s2 $end
$var wire 1 2 grp1_tr $end
$var wire 3 3 ifs_cfg [2:0] $end
$var wire 3 4 lpf_cfg [2:0] $end
$var wire 1 5 lpw_on $end
$var wire 1 6 ref_tft_pd $end
$var wire 3 7 vcoarse [2:0] $end
$upscope $end

$upscope $end

$upscope $end

Here is vcd_info: (I tried with .hier 0 ... it doesn't work at all ... simulator stops with error "can't load vcd file" or something like this)

.hier 1
.vih 1.8
.vil 0.0

.scope tb_top.inst_as2005_left.ANA

.alias tb_top.inst_as2005_left.ANA.grp1_blo_on grp1_blo_on
.alias tb_top.inst_as2005_left.ANA.grp1_cds1 grp1_cds1
.alias tb_top.inst_as2005_left.ANA.grp1_cds2 grp1_cds2
.alias tb_top.inst_as2005_left.ANA.grp1_clk grp1_clk
.alias tb_top.inst_as2005_left.ANA.grp1_irst grp1_irst
.alias tb_top.inst_as2005_left.ANA.grp1_lpf_on grp1_lpf_on
.alias tb_top.inst_as2005_left.ANA.grp1_s1 grp1_s1
.alias tb_top.inst_as2005_left.ANA.grp1_s2 grp1_s2
.alias tb_top.inst_as2005_left.ANA.grp1_tr grp1_tr

.alias tb_top.inst_as2005_left.ANA.lpw_on lpw_on
.alias tb_top.inst_as2005_left.ANA.afe_pd afe_pd
.alias tb_top.inst_as2005_left.ANA.ref_tft_pd ref_tft_pd
*.alias tb_top.inst_as2005_left.ANA.ifs_cfg[2:0] ifs_cfg<2:0>
*.alias tb_top.inst_as2005_left.ANA.cap[2:0] cap<2:0>
*.alias tb_top.inst_as2005_left.ANA.comp1[2:0] comp1<2:0>
*.alias tb_top.inst_as2005_left.ANA.comp2[2:0] comp2<2:0>
*.alias tb_top.inst_as2005_left.ANA.vcoarse[2:0] vcoarse<2:0>
*.alias tb_top.inst_as2005_left.ANA.cal_dac[7:0] cal_dac<7:0>
.alias tb_top.inst_as2005_left.ANA.cal_load cal_load
.alias tb_top.inst_as2005_left.ANA.cal_on cal_on
.alias tb_top.inst_as2005_left.ANA.cal_readout cal_readout

.alias tb_top.inst_as2005_left.ANA.*[*] *<*>

.out grp1_adc<50:0>
.in grp1_blo_on
.in grp1_cds1
.in grp1_cds2
.in grp1_clk
.in grp1_irst
.in grp1_lpf_on
.in grp1_s1
.in grp1_s2
.in grp1_tr

.in lpw_on
.in afe_pd
.in ref_tft_pd
.in lpf_cfg<2:0>
.in ifs_cfg<2:0>
.in cap<2:0>
.in comp1<2:0>
.in comp2<2:0>
.in vcoarse<2:0>
.in cal_dac<7:0>
.in cal_load
.in cal_on
.in cal_readout

With .hier 1 it runs but in Spectre log I see this:

Notice from spectre during topology check.
No connections to node `tb_top.inst_as2005_left.ANA.grp1_adc<50>'.
No connections to node `tb_top.inst_as2005_left.ANA.grp1_adc<49>'.
No connections to node `tb_top.inst_as2005_left.ANA.grp1_adc<48>'.
No connections to node `tb_top.inst_as2005_left.ANA.grp1_adc<47>'.
No connections to node `tb_top.inst_as2005_left.ANA.grp1_adc<46>'.
Further occurrences of this notice will be suppressed.
Only one connection to the following 71 nodes:
cal_daq<7>
cal_daq<6>
cal_daq<5>
cal_daq<4>
cal_daq<3>
Further occurrences of this notice will be suppressed.
No DC path from node `I8.DSLICE.CSA.ABLOOM.sleep' to ground, Gmin installed to provide path.
No DC path from node `grp1_clk' to ground, Gmin installed to provide path.
No DC path from node `cal_dac[7]' to ground, Gmin installed to provide path.
No DC path from node `cal_dac[6]' to ground, Gmin installed to provide path.
No DC path from node `cal_dac[5]' to ground, Gmin installed to provide path.
Further occurrences of this notice will be suppressed.

Actually I don't know what is connected and what isn't because only part of "only one connection" notices is displayed.

Does exist a way to display all of them ?

Thanks.

Without the data, it's pretty hard to debug this. You've only included part of the VCD file, and I don't know what your netlist looks like either. I think you've aliased the names incorrectly, probably. You have cal_daq<> and cal_dac[] names in the report - the single connection means that there's a single connection, so it's really not clear if it's connected properly from the messages alone.

I'm sure this would be easy to solve with access to the data. If you can't share it here, please contact customer support.

Regards,

Andrew.

Thanks Andrew,

I can share, but I didn't find a way to attach it ... only video/image types are accepted

Well, after correcting cal_dac name I see that there is no proble (except mapping one wire form vcd bus, i.e. grp1_adc[50:0] to a signal in schematic) there is no problem, it's Ok.

All other "no connect" warnings concern schematic internal nodes (I saw it after after activating an optinon allowing to display all warnings).

Nevertheless the signals at VCD-schematic interface do not evolve as they should, i.e. I don't see clock

You can upload other files via Insert Image/Video/File. You might need to give the file a ".txt" suffix though.

Perhaps with an example I can look and see what you mean by this:

pyohayo said:

Nevertheless the signals at VCD-schematic interface do not evolve as they should, i.e. I don't see clock

Andrew

Here it is:

Perhaps with an example I can look and see what you mean by this:

I mean I see clock (i.e.grp1_clk)  in SimVision, but don't see it in Virtuoso Graph window once simulation terminated.

file_vcd.txt

Here is as it should look:

Here is as it should look:

And here are the same signals in Virtuoso:

Resolved.

In SimVision I've exported range 700us ... 1100us hoping that time will be shifted to 0 ... 400us, that wasn't the case.