I am doing AMS simulation using the version 6.1.5. I am using 65nm TSMC. When I run simulation it fails because of the mim caps that I used in analog parts. And when I replace the mim caps with the ideal caps it works.
Does anyone know what could be the problem?
Mostafa A said:When I run simulation it fails because of the mim caps that I used in analog parts. And when I replace the mim caps with the ideal caps it works.
Are you using an extracted view of the "analog part"? Often MIM capacitor models are not include in an extracted view based netlist as they are composed of interconnect components. However, in a schematic netlist based simulation, a discrete model exists for a MIM capacitor. I am wondering if you are using an extracted view of the "analog parts" as the manner in which they are simulated, from a component perspective, are totally different.
For example, if models of your interconnect are not available, but an ideal capacitor model is available, your simulation will fail when an interconnect based capacitor is included in an extracted view based netlist.
This is only a guess based on your few sentences and may not be relevant. However, the thought came to mind and thought perhaps I would pass it along.
Thank you dear Shawn for reply. I didn't get your point by "extracted view". I run the simulation in "config" environment. The circuit has some analog parts (which includes MIM caps , transistors, and resistors) and some digital blocks which are verilog described.