I am doing AMS simulation using the version 6.1.5. I am using 65nm TSMC. When I run simulation it fails because of the mim caps that I used in analog parts. And when I replace the mim caps with the ideal caps it works.
Does anyone know what could be the problem?
Mostafa A said:When I run simulation it fails because of the mim caps that I used in analog parts. And when I replace the mim caps with the ideal caps it works.
Are you using an extracted view of the "analog part"? Often MIM capacitor models are not include in an extracted view based netlist as they are composed of interconnect components. However, in a schematic netlist based simulation, a discrete model exists for a MIM capacitor. I am wondering if you are using an extracted view of the "analog parts" as the manner in which they are simulated, from a component perspective, are totally different.
For example, if models of your interconnect are not available, but an ideal capacitor model is available, your simulation will fail when an interconnect based capacitor is included in an extracted view based netlist.
This is only a guess based on your few sentences and may not be relevant. However, the thought came to mind and thought perhaps I would pass it along.
Thank you dear Shawn for reply. I didn't get your point by "extracted view". I run the simulation in "config" environment. The circuit has some analog parts (which includes MIM caps , transistors, and resistors) and some digital blocks which are verilog described.
Mostafa A said:I didn't get your point by "extracted view". I run the simulation in "config" environment.
I am sorry I confused you and was not clear Mostafa!
In other words, is the config view of the "analog parts" that contains the MIM capacitors set to a use a schematic view of the "analog parts" - or is it set to a use a layout based view to create your config netlist? The latter will include parasitic elements of the layout not present in a schematic view based netlist.
Does this help to clarify my comment?
Don't mention it.
As I see the I have schematic view of the analog parts in the config (Attached)
Mostafa A said:When I run simulation it fails because of the mim caps that I used in analog parts
"fails" is a bit non-specific so it's pretty hard to give advice without more detail. How exactly does it fail? What is the error you get? Is it during netlisting? Is it during simulation? What is the error message? Which simulator version are you using (this should appear in the simulator log file). On the SImulation->Netlist and Run Options form are using using CellView-based or OSS netlisting?
I would strongly recommend you use a more recent IC version than IC615 - then you can take advantage of the newer Unified Netlister which is generally more robust. So I would recommend switching to IC6.1.8 and XCELIUM20.03 or XCELIUM20.09 (XCELIUM replaced INCISIVE a few years back).