AMS Simulation: Use SystemVerilog module instantiating other submodules in SystemVerilog

Hello,

First, thanks for reading this post !

I am working on a mixed signal simulation using ADE explorer and AMS simulator.

In the top design I have a module A I want to instantiate as a systemVerilog object. in the sv file this module include a submodule B also defined in sv.

Both modules are defined in the same file

/* Start file*/

module A();

  B(ports...)

endmodule

module B();

description ....

endmodule

/*end file*/

When I generate the netlist it fails telling that B (here muxReadX) is not defined in config view ....

Then I tryed to use a separate sv file for B in to use the `include "pathToB" method (adding the path to B in the ams simulator option) but I have the same error.

/* Start file*/

`include "path_to_B"

module A();

  B(ports...)

endmodule

/*end file*/

Then I created a library named SYSTEMVERILOG_lib in which I store the sv description. I added it in the library list of my config view but it still does not find it (address_decoder is found and I do not know why it is different here)

Do you have any idea on how to solve this ?

I have also to precise that I do not have this issue with sv module that does not call submodule.

I am using IC23.1

I have already seen this post but it was not helpful:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000006DdhMUAS&pageName=ArticleContent

 How to include Verilog functional files in Virtuoso Hierarchy Editor for SDF Simulation 

 In AMS simulation, for verilog, how to use a module in a top module? 

I would be glad to give more precision if needed.

Thank you in advance for your help

Mathieu