simulating node capacitance charging

You could use the captab capability to report the instantaneous capacitance operating point info at the the times in question. The easiest way to do this is first to enable a dc analysis with the captab settings (strictly speaking it's not the DC analysis, but an info analysis, and so you could potentially use a row in the Save circuit information analysis table to add a new captab output - but for now I'll just showing doing it from dc). This is on the DC options form:

Then on the transient options form, enable infotimes to be the times you want to output the capacitance info - and give the name of the captab info analysis (the name is generated automatically by checking the captab on the DC options above - the name I've given here is the name that appears in the netlist):

Then after running the simulations, under Results->Print->Capacitance Table you'll get this - with a cyclic field at the top to pick the time you wish to look at:

Regards,

Andrew.

Hello Andrew,so at a certain time it shows me the capacitance.

I found the CAPTAB in Transient->options so its time domain .

Maybe AC CAPTAB is better ? because capacitance at DC is open circuit.

How can i do CAPTAB at AC?

Thanks 

Thanks 

Andrew Beckett said:

but for now I'll just showing doing it from dc

yefJ said:

is there an article  with Cadence virtuoso implementation where i cant see how to plan a TG that will get threw my data  when the clock rises?

If I understand your initial objective, which you stated as "i am trying to build an RF frequency D FlipFlop as shown bellow", I think there is an error in your schematic diagram. I have modified your diagram and included it below to illustrate what I think you need to simulate. When your input TG is low impedance, TG1 is high impedance and node Q will charge to the D input voltage and the output of the inverter with input Q will be QN. When input TG becomes high impedance, TG1 will become low impedance and it will allow the feedback inverter to force node Q to the voltage it had when TG was low impedance.

Does this make more sense now yefj?

yefJ said:

is there an article  with Cadence virtuoso implementation where i cant see how to plan a TG that will get threw my data  when the clock rises?

If I understand your initial objective, which you stated as "i am trying to build an RF frequency D FlipFlop as shown bellow", I think there is an error in your schematic diagram. I have modified your diagram and included it below to illustrate what I think you need to simulate. When your input TG is low impedance, TG1 is high impedance and node Q will charge to the D input voltage and the output of the inverter with input Q will be QN. When input TG becomes high impedance, TG1 will become low impedance and it will allow the feedback inverter to force node Q to the voltage it had when TG was low impedance.

Does this make more sense now yefj?