• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      oldmouldy
      oldmouldy 55 Points
    • 2
      steve
      steve 25 Points
    • 2
      excellon1
      excellon1 25 Points
    • 4
      JCTEYSSIER0
      JCTEYSSIER0 20 Points
    • 4
      Robert Finley
      Robert Finley 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,848 Points
    • 2
      oldmouldy
      oldmouldy 11,055 Points
    • 3
      eDave
      eDave 7,631 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,226 Points
    • 5
      redwire
      redwire 5,188 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    Text Line Space Not as Documented

    Category: PCB Design

    By Allan M

    •

    updated over 15 years ago by redwire

    1 replies • 13895 views
  • Discussion

    allegro v16.3(v16.2) opengel ... bug ???

    Category: PCB Design

    By min sook

    •

    updated over 15 years ago by oldmouldy

    1 replies • 750 views
  • Discussion

    REGARDING MICROViA

    Category: PCB Design

    By girish

    •

    updated over 15 years ago by Robert Finley

    3 replies • 14644 views
  • Discussion

    Net list from CIS capture

    Category: PCB Design

    By archive

    •

    updated over 15 years ago by gregp

    2 replies • 13444 views
  • Discussion

    I lost my via class on the options for PCB Editor 16.2

    Category: PCB Design

    By kanonfodder

    •

    updated over 15 years ago by kanonfodder

    1 replies • 12807 views
  • Discussion

    Capture CIS netlist error to PCB Editor

    Category: PCB Design

    By SharonPaige

    •

    updated over 15 years ago by otto9otto

    9 replies • 17300 views
  • Discussion

    Center line not showing up

    Category: PCB Design

    By gonuclear

    •

    updated over 15 years ago by BillZ

    1 replies • 12907 views
  • Discussion

    Bond Wire Width in APD16.2

    Category: Allegro X PCB Editor

    By Alice 2009

    •

    updated over 15 years ago by Alice 2009

    3 replies • 13510 views
  • Discussion

    Auto silkscreen does not work with filled shapes v16.3

    Category: PCB Design

    By shangwu

    •

    updated over 15 years ago by mcatramb91

    1 replies • 13118 views
  • Discussion

    Lightning protection.

    Category: PCB Design

    By JPeter

    •

    updated over 15 years ago by KEN13

    6 replies • 16653 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information