• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      MZ20250602835
      MZ20250602835 51 Points
    • 2
      steve
      steve 40 Points
    • 3
      Robert Finley
      Robert Finley 30 Points
    • 4
      JCTEYSSIER0
      JCTEYSSIER0 25 Points
    • 5
      RJ202412171240
      RJ202412171240 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,848 Points
    • 2
      oldmouldy
      oldmouldy 11,015 Points
    • 3
      eDave
      eDave 7,576 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,236 Points
    • 5
      redwire
      redwire 5,113 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    Finding the width of a thermal cline

    Category: Allegro X PCB Editor

    By Geoff

    •

    updated over 10 years ago by Geoff

    2 replies • 14061 views
  • Discussion

    how to name XNet in Allegro Schematics Capture?

    Category: PCB Design

    By Kumar Motorola

    •

    updated over 10 years ago by Kumar Motorola

    2 replies • 16146 views
  • Discussion

    Mystery properties

    Category: PCB Design

    By RogerM

    •

    updated over 10 years ago by RogerM

    6 replies • 18218 views
  • Discussion

    #1 WARNING(SPMHNI-316): Property warning detected.

    Category: PCB Design

    By maberu

    •

    updated over 10 years ago by maberu

    3 replies • 2275 views
  • Discussion

    $pnn property

    Category: PCB Design

    By ahmetozsoy

    •

    updated over 10 years ago by maberu

    3 replies • 15628 views
  • Discussion

    Intertool Cpmmunication Problem

    Category: PCB Design

    By zainada

    •

    updated over 10 years ago by steve

    1 replies • 14039 views
  • Discussion

    .

    Category: Allegro X APD

    By blankman

    •

    updated over 10 years ago by blankman

    2 replies • 2166 views
  • Discussion

    Test Point and shapes

    Category: PCB Design

    By DAAS

    •

    started over 10 years ago

    0 replies • 12980 views
  • Discussion

    Proper routing of trace between bumps (WLCSP or FC design)

    Category: Allegro X APD

    By Nomer

    •

    started over 10 years ago

    0 replies • 13757 views
  • Discussion

    Find the smallest part of a given shape or polygon

    Category: Allegro X PCB Editor

    By eDaNoy

    •

    updated over 10 years ago by eDaNoy

    2 replies • 13926 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information