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PCB Design & IC Packaging (Allegro X)

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Forum - Thread List

Latest Posts

  • Discussion

    how to draw a line in Concept HDL?

    Category: PCB Design

    By peter zhu

    •

    updated over 10 years ago by Theodor I.

    11 replies • 25433 views
  • Discussion

    Orcad Capture: how to set "find" in entire design by default or all the times

    Category: PCB Design

    By Reja

    •

    started over 10 years ago

    0 replies • 2340 views
  • Discussion

    Issue with duplicated Pspice model -Full version of Cadence 16.5

    Category: PCB Design

    By TOM12345

    •

    updated over 10 years ago by tltoth

    3 replies • 4461 views
  • Discussion

    Re-numbering pins

    Category: PCB Design

    By morgan23

    •

    updated over 10 years ago by morgan23

    2 replies • 16354 views
  • Discussion

    Issue with duplicated Pspice model -Full version of Cadence 16.5

    Category: PCB Design

    By TOM12345

    •

    started over 10 years ago

    0 replies • 370 views
  • Discussion

    DRC Troubles. Same net spacing. Thermal connects

    Category: PCB Design

    By Delf13

    •

    updated over 10 years ago by Delf13

    15 replies • 14672 views
  • Discussion

    Create custom VAC-Source in pspice

    Category: PCB Design

    By komase

    •

    updated over 10 years ago by komase

    2 replies • 18677 views
  • Discussion

    Need help in verilog file creation

    Category: PCB Design

    By mahee424

    •

    updated over 10 years ago by wijnaldum

    1 replies • 14673 views
  • Discussion

    Unable to open .sch file in Orcad Lite 16.6.

    Category: PCB Design

    By Ansh15

    •

    updated over 10 years ago by luvishis

    4 replies • 17571 views
  • Discussion

    DRC ERROR LINE TO SHAPE SPACING

    Category: PCB Design

    By aBhi22

    •

    updated over 10 years ago by oldmouldy

    4 replies • 15538 views
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