• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      CF202606104231
      CF202606104231 45 Points
    • 2
      Electro Node
      Electro Node 40 Points
    • 3
      avant
      avant 30 Points
    • 4
      SG20260713408
      SG20260713408 20 Points
    • 4
      TL202608111936
      TL202608111936 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,528 Points
    • 2
      oldmouldy
      oldmouldy 10,615 Points
    • 3
      eDave
      eDave 7,286 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,231 Points
    • 5
      redwire
      redwire 4,213 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    Regarding reference planes

    Category: PCB Design

    By gowthaman90d

    •

    updated over 10 years ago by MikeVeal

    4 replies • 16927 views
  • Discussion

    how to draw a line in Concept HDL?

    Category: PCB Design

    By peter zhu

    •

    updated over 10 years ago by Theodor I.

    11 replies • 26124 views
  • Discussion

    Orcad Capture: how to set "find" in entire design by default or all the times

    Category: PCB Design

    By Reja

    •

    started over 10 years ago

    0 replies • 2461 views
  • Discussion

    Issue with duplicated Pspice model -Full version of Cadence 16.5

    Category: PCB Design

    By TOM12345

    •

    updated over 10 years ago by tltoth

    3 replies • 4621 views
  • Discussion

    Re-numbering pins

    Category: PCB Design

    By morgan23

    •

    updated over 10 years ago by morgan23

    2 replies • 16675 views
  • Discussion

    Issue with duplicated Pspice model -Full version of Cadence 16.5

    Category: PCB Design

    By TOM12345

    •

    started over 10 years ago

    0 replies • 405 views
  • Discussion

    DRC Troubles. Same net spacing. Thermal connects

    Category: PCB Design

    By Delf13

    •

    updated over 10 years ago by Delf13

    15 replies • 15342 views
  • Discussion

    Create custom VAC-Source in pspice

    Category: PCB Design

    By komase

    •

    updated over 10 years ago by komase

    2 replies • 18894 views
  • Discussion

    Need help in verilog file creation

    Category: PCB Design

    By mahee424

    •

    updated over 10 years ago by wijnaldum

    1 replies • 14766 views
  • Discussion

    Unable to open .sch file in Orcad Lite 16.6.

    Category: PCB Design

    By Ansh15

    •

    updated over 10 years ago by luvishis

    4 replies • 17788 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information