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  • Discussion

    Differences between APD & CDNSIP

    8280 views
    5 replies
    Latest over 5 years ago
    by sidm
  • Discussion

    Dynamic phase tolerance

    18894 views
    3 replies
    Latest over 5 years ago
    by steve
  • Not Answered

    OrCAD Capture 17.40.008 Very Slow and Clunky Startup 0

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    Latest over 5 years ago
    by cstocci
  • Not Answered

    Schematic Symbols: How to hide pins on 17.2 S057 0

    25630 views
    7 replies
    Latest over 5 years ago
    by DavidH172
  • Discussion

    Help with understanding componenet in PCB

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    0 replies
    Started over 5 years ago
    by Yachel
  • Discussion

    TCL - Get the Most Recent Part Locked

    2528 views
    1 reply
    Latest over 5 years ago
    by Kalars
  • Discussion

    17.4 compatibility warning

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    3 replies
    Latest over 5 years ago
    by TravelinGuy
  • Discussion

    Show all same sized drills

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    2 replies
    Latest over 5 years ago
    by Mabr86
  • Discussion

    Get the key of table entry found by index

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    3 replies
    Latest over 5 years ago
    by B Bruekers
  • Discussion

    Replace package symbols without changing netlist? Locked

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    by redwire
  • Discussion

    Assign net name in static shape

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    2 replies
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    by B Bruekers
  • Discussion

    Padstack editor in 17.4 trial version

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    4 replies
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    by Joel88
  • Discussion

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    1 reply
    Latest over 5 years ago
    by oldmouldy
  • Discussion

    Ravel Coding

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    0 replies
    Started over 5 years ago
    by sidm
  • Discussion

    How to automatedly close/select options of alert window in allegro system using Allegro .src or python scripts?

    5619 views
    3 replies
    Latest over 5 years ago
    by Yun777
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