• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    FIles for nmDRC in calibre for gpdk180nm ? Locked

    3941 views
    1 reply
    Latest over 1 year ago
    by Andrew Beckett
  • Answered

    Want to fetch the Part Reference and Designator in OrCAD Capture CIS 0

    2121 views
    1 reply
    Latest over 1 year ago
    by CadAP
  • Discussion

    Optimize Component Placement in OrCAD X Presto

    1208 views
    0 replies
    Started over 1 year ago
    by aniju
  • Discussion

    Advantages of Via Stitching in PCB Design

    5619 views
    0 replies
    Started over 1 year ago
    by mahimag
  • Discussion

    Fixing path object off-grid Locked

    3897 views
    1 reply
    Latest over 1 year ago
    by TzuYun Chang
  • Discussion

    Set Interactive history name to follow the previous test run Locked

    5272 views
    2 replies
    Latest over 1 year ago
    by HYKen
  • Discussion

    Regarding issue while using Auto Via Locked

    3791 views
    2 replies
    Latest over 1 year ago
    by skillEater
  • Suggested Answer

    how to get the data of component place(component place Top/Bottom on pcb) 0

    1107 views
    2 replies
    Latest over 1 year ago
    by NG202409088131
  • Discussion

    Find the calibrated code in DC before moving to next Test Locked

    3365 views
    0 replies
    Started over 1 year ago
    by HongJian
  • Discussion

    Defining custom sigType Locked

    3680 views
    1 reply
    Latest over 1 year ago
    by Andrew Beckett
  • Discussion

    Cell layout bigger than PR Boundary Locked

    5257 views
    1 reply
    Latest over 1 year ago
    by Andrew Beckett
  • Discussion

    Importing package in AMS simulation Locked

    4322 views
    0 replies
    Started over 1 year ago
    by MostafaAbedi
  • Answered

    Allegro free view setup - change mouse settings +1

    3112 views
    3 replies
    Latest over 1 year ago
    by cedar
  • Discussion

    Missing pins in symbol creation of systemVerilog module Locked

    6258 views
    4 replies
    Latest over 1 year ago
    by MostafaAbedi
  • Discussion

    Tracing a net connection from M1 to the top most metal in layout using SKILL script Locked

    5838 views
    7 replies
    Latest over 1 year ago
    by MSP032
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information