• Discussion

  Tran simulation results can't be saved when using XPS MS and enabling post-layout optimization? Locked

  2344 views
  1 reply
  Latest over 1 year ago
  by Andrew Beckett
• Discussion

  Can not change instance in schematic view Locked

  6258 views
  2 replies
  Latest over 1 year ago
  by Omar Ghazal
• Discussion

  Fail to generate netlist as cell view specified to a SPICE file in Hierarchy Editor Locked

  7861 views
  4 replies
  Latest over 1 year ago
  by Leo66
• Discussion

  UVM Adapter for Pipelined protocols like AHB, AXI etc Locked

  6574 views
  0 replies
  Started over 1 year ago
  by VeeJ
• Not Answered

  Constrain Manager: LayerSubTypes.xml could not be read 0

  9388 views
  8 replies
  Latest over 1 year ago
  by toldav
• Discussion

  XF Analysis: How to save transfer function from only certain sources? Locked

  5584 views
  2 replies
  Latest over 1 year ago
  by Matthew Love
• Discussion

  Virtuoso adexl relxpert aging simulation is disabled Locked

  5210 views
  0 replies
  Started over 1 year ago
  by Holz
• Discussion

  Creating data.dm for schematic and symbol Locked

  6818 views
  3 replies
  Latest over 1 year ago
  by Andrew Beckett
• Discussion

  Problem with using a genvar in if statement in Verilog-a Locked

  5648 views
  0 replies
  Started over 2 years ago
  by Esmee Tackx
• Discussion

  Ignore dummies in PVS using GPDK 45nm [solved] Locked

  8008 views
  6 replies
  Latest over 2 years ago
  by RobMan
• Discussion

  Report power in Genus using user defined default switching activity Locked

  6464 views
  0 replies
  Started over 2 years ago
  by gops
• Discussion

  Unable to open the waveform file `ecg/.csv'. Ensure that the specified file or directory exists. Locked

  1589 views
  1 reply
  Latest over 2 years ago
  by Andrew Beckett
• Discussion

  Re-evaluating an "eval err" expression after simulation Locked

  5230 views
  4 replies
  Latest over 2 years ago
  by RuihW
• Not Answered

  allegro design entry cis 17.4 - export pdf issue 0

  5052 views
  10 replies
  Latest over 2 years ago
  by Ulf K
• Discussion

  General Considerations when routing DDR nets in high-speed design!

  5460 views
  0 replies
  Started over 2 years ago
  by VVRD